feat(intel): add macro to switch between different UART PORT

HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using parameter PLAT_INTEL_UART_BASE

This patch also fixing the plat_helpers.S where the
UART BASE is hardcoded to PLAT_UART0_BASE. It is then
switched to CRASH_CONSOLE_BASE.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f

plat/intel/soc/agilex/bl2_plat_setup.c

@@ -71,8 +71,8 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
 
 	watchdog_init(get_wdt_clk());
 
-	console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
+	console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(),
-		&console);
+		PLAT_BAUDRATE, &console);
 
 	socfpga_delay_timer_init();
 	init_ncore_ccu();

plat/intel/soc/agilex/bl31_plat_setup.c

@@ -41,8 +41,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 	mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
 
-	console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
+	console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
-		&console);
+		PLAT_BAUDRATE, &console);
 	/*
 	 * Check params passed from BL31 should not be NULL,
 	 */

plat/intel/soc/common/aarch64/plat_helpers.S

@@ -102,7 +102,7 @@ endfunc plat_get_my_entrypoint
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_init
-	mov_imm	x0, PLAT_UART0_BASE
+	mov_imm	x0, CRASH_CONSOLE_BASE
 	mov_imm	x1, PLAT_UART_CLOCK
 	mov_imm	x2, PLAT_BAUDRATE
 	b	console_16550_core_init
@@ -116,7 +116,7 @@ endfunc plat_crash_console_init
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_putc
-	mov_imm x1, PLAT_UART0_BASE
+	mov_imm x1, CRASH_CONSOLE_BASE
 	b	console_16550_core_putc
 endfunc plat_crash_console_putc
 

plat/intel/soc/common/include/platform_def.h

@@ -168,6 +168,7 @@
 #define PLAT_UART1_BASE		(0xFFC02100)
 
 #define CRASH_CONSOLE_BASE	PLAT_UART0_BASE
+#define PLAT_INTEL_UART_BASE	PLAT_UART0_BASE
 
 #ifndef SIMICS_BUILD
 #define PLAT_BAUDRATE		(115200)

plat/intel/soc/n5x/bl31_plat_setup.c

@@ -42,8 +42,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 	mmio_write_64(PLAT_SEC_ENTRY, 0);
 
-	console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
+	console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
-		&console);
+		PLAT_BAUDRATE, &console);
 	/*
 	 * Check params passed from BL31 should not be NULL,
 	 */

plat/intel/soc/stratix10/bl2_plat_setup.c

@@ -69,8 +69,8 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
 
 	watchdog_init(get_wdt_clk());
 
-	console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
+	console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(),
-		&console);
+		PLAT_BAUDRATE, &console);
 
 	socfpga_emac_init();
 	socfpga_delay_timer_init();

plat/intel/soc/stratix10/bl31_plat_setup.c

@@ -49,8 +49,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 	mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
 
-	console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
+	console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
-		&console);
+		PLAT_BAUDRATE, &console);
 	/*
 	 * Check params passed from BL31 should not be NULL,
 	 */