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Cortex-A57: Implement workaround for erratum 859972 

Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.

Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
pull/1092/head
Eleanor Bonnici 7 years ago
committed by Jeenu Viswambharan
parent
5457874575
commit
45b52c202f
6 changed files with 79 additions and 2 deletions
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  1. 8
      docs/cpu-specific-build-macros.rst
  2. 1
      include/lib/cpus/aarch32/cortex_a57.h
  3. 1
      include/lib/cpus/aarch64/cortex_a57.h
  4. 32
      lib/cpus/aarch32/cortex_a57.S
  5. 31
      lib/cpus/aarch64/cortex_a57.S
  6. 8
      lib/cpus/cpu-ops.mk

8
docs/cpu-specific-build-macros.rst
View File

@ -30,7 +30,8 @@ errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor nam
is for example ``A57`` for the ``Cortex_A57`` CPU.
Refer to the section *CPU errata status reporting* in
`Firmware Design guide`_ for information on to write errata workaround functions.
`Firmware Design guide`_ for information on how to write errata workaround
functions.
All workarounds are disabled by default. The platform is responsible for
enabling these workarounds according to its requirement by defining the
@ -98,6 +99,9 @@ For Cortex-A57, following errata build flags are defined :
- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
CPU Specific optimizations
--------------------------
@ -131,7 +135,7 @@ architecture that can be enabled by the platform as desired.
*Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.*
.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf
.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf
.. _Firmware Design guide: firmware-design.rst
.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf

1
include/lib/cpus/aarch32/cortex_a57.h
View File

@ -49,6 +49,7 @@
#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
#define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25)
#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)

1
include/lib/cpus/aarch64/cortex_a57.h
View File

@ -49,6 +49,7 @@
#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)

32
lib/cpus/aarch32/cortex_a57.S
View File

@ -306,6 +306,32 @@ func check_errata_833471
b cpu_rev_var_ls
endfunc check_errata_833471
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #859972.
* This applies only to revision <= r1p3 of Cortex A57.
* Inputs:
* r0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: r0-r3
* ---------------------------------------------------
*/
func errata_a57_859972_wa
mov r2, lr
bl check_errata_859972
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_859972_wa
func check_errata_859972
mov r1, #0x13
b cpu_rev_var_ls
endfunc check_errata_859972
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A57.
* Shall clobber: r0-r6
@ -356,6 +382,11 @@ func cortex_a57_reset_func
bl errata_a57_833471_wa
#endif
#if ERRATA_A57_859972
mov r0, r4
bl errata_a57_859972_wa
#endif
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
@ -487,6 +518,7 @@ func cortex_a57_errata_report
report_errata ERRATA_A57_828024, cortex_a57, 828024
report_errata ERRATA_A57_829520, cortex_a57, 829520
report_errata ERRATA_A57_833471, cortex_a57, 833471
report_errata ERRATA_A57_859972, cortex_a57, 859972
pop {r12, lr}
bx lr

31
lib/cpus/aarch64/cortex_a57.S
View File

@ -304,6 +304,30 @@ func check_errata_833471
b cpu_rev_var_ls
endfunc check_errata_833471
/* --------------------------------------------------
* Errata Workaround for Cortex A57 Errata #859972.
* This applies only to revision <= r1p3 of Cortex A57.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber:
* --------------------------------------------------
*/
func errata_a57_859972_wa
mov x17, x30
bl check_errata_859972
cbz x0, 1f
mrs x1, CORTEX_A57_CPUACTLR_EL1
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH
msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_859972_wa
func check_errata_859972
mov x1, #0x13
b cpu_rev_var_ls
endfunc check_errata_859972
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A57.
* Shall clobber: x0-x19
@ -354,6 +378,11 @@ func cortex_a57_reset_func
bl errata_a57_833471_wa
#endif
#if ERRATA_A57_859972
mov x0, x18
bl errata_a57_859972_wa
#endif
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
@ -483,6 +512,8 @@ func cortex_a57_errata_report
report_errata ERRATA_A57_828024, cortex_a57, 828024
report_errata ERRATA_A57_829520, cortex_a57, 829520
report_errata ERRATA_A57_833471, cortex_a57, 833471
report_errata ERRATA_A57_859972, cortex_a57, 859972
ldp x8, x30, [sp], #16
ret

8
lib/cpus/cpu-ops.mk
View File

@ -91,6 +91,10 @@ ERRATA_A57_829520 ?=0
# only to revision <= r1p2 of the Cortex A57 cpu.
ERRATA_A57_833471 ?=0
# Flag to apply erratum 855972 workaround during reset. This erratum applies
# only to revision <= r1p3 of the Cortex A57 cpu.
ERRATA_A57_859972 ?=0
# Process ERRATA_A53_826319 flag
$(eval $(call assert_boolean,ERRATA_A53_826319))
$(eval $(call add_define,ERRATA_A53_826319))
@ -143,6 +147,10 @@ $(eval $(call add_define,ERRATA_A57_829520))
$(eval $(call assert_boolean,ERRATA_A57_833471))
$(eval $(call add_define,ERRATA_A57_833471))
# Process ERRATA_A57_859972 flag
$(eval $(call assert_boolean,ERRATA_A57_859972))
$(eval $(call add_define,ERRATA_A57_859972))
# Errata build flags
ifneq (${ERRATA_A53_843419},0)
TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419

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