From 46e92f2862326cbe57acecb2d0f3c2ffbcc176d2 Mon Sep 17 00:00:00 2001 From: Boyan Karatotev Date: Thu, 13 Oct 2022 13:51:05 +0100 Subject: [PATCH] fix(sme): add missing ISBs EL3 is configured to trap accesses to SME registers (via CPTR_EL3.ESM=0). To allow SME instructions, this needs to be temporarily disabled before changing system registers. If the PE delays the effects of writes to system registers then accessing the SME registers will trap without an isb. This patch adds the isb to restore functionality. Signed-off-by: Boyan Karatotev Change-Id: I8ee5ecaec978dde2525631daa682a182ad8f7f04 --- lib/extensions/sme/sme.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c index 958b62347..ec8cca82b 100644 --- a/lib/extensions/sme/sme.c +++ b/lib/extensions/sme/sme.c @@ -58,6 +58,7 @@ void sme_enable(cpu_context_t *context) /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ cptr_el3 = read_cptr_el3(); write_cptr_el3(cptr_el3 | ESM_BIT); + isb(); /* * Set the max LEN value and FA64 bit. This register is set up globally @@ -73,6 +74,7 @@ void sme_enable(cpu_context_t *context) /* Reset CPTR_EL3 value. */ write_cptr_el3(cptr_el3); + isb(); /* Enable SVE/FPU in addition to SME. */ sve_enable(context);