From 4789cf66af0560900b088e03968bc2fc83d1f330 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Mon, 2 Aug 2021 13:22:32 -0500 Subject: [PATCH] errata: workaround for Neoverse V1 errata 1774420 Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and r1p0 of the V1 processor core. It is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: Lauren Wehrmeister Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123 --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/neoverse_v1.h | 1 + lib/cpus/aarch64/neoverse_v1.S | 40 +++++++++++++++++++++-- lib/cpus/cpu-ops.mk | 8 +++++ 4 files changed, 50 insertions(+), 3 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 949845ab8..a9d6e371b 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -325,6 +325,10 @@ For Neoverse N1, the following errata build flags are defined : For Neoverse V1, the following errata build flags are defined : +- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 + CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed + in r1p1. + - ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed in r1p1. diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h index cea26599f..2c9bfda5b 100644 --- a/include/lib/cpus/aarch64/neoverse_v1.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -13,6 +13,7 @@ * CPU Extended Control register specific definitions. ******************************************************************************/ #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) /******************************************************************************* * CPU Power Control register specific definitions diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index cee0bb733..62b92b2c3 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2021, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,6 +21,34 @@ #error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #1774420. + * This applies to revisions r0p0 and r1p0, fixed in r1p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_1774420_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1774420 + cbz x0, 1f + + /* Set bit 53 in CPUECTLR_EL1 */ + mrs x1, NEOVERSE_V1_CPUECTLR_EL1 + orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 + msr NEOVERSE_V1_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_neoverse_v1_1774420_wa + +func check_errata_1774420 + /* Applies to r0p0 and r1p0. */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1774420 + /* -------------------------------------------------- * Errata Workaround for Neoverse V1 Errata #1791573. * This applies to revisions r0p0 and r1p0, fixed in r1p1. @@ -35,9 +63,9 @@ func errata_neoverse_v1_1791573_wa cbz x0, 1f /* Set bit 2 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 + mrs x1, NEOVERSE_V1_ACTLR2_EL1 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 - msr NEOVERSE_V1_ACTLR2_EL1, x1 + msr NEOVERSE_V1_ACTLR2_EL1, x1 isb 1: ret x17 @@ -134,6 +162,7 @@ func neoverse_v1_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 @@ -149,6 +178,11 @@ func neoverse_v1_reset_func msr SSBS, xzr isb +#if ERRATA_V1_1774420 + mov x0, x18 + bl errata_neoverse_v1_1774420_wa +#endif + #if ERRATA_V1_1791573 mov x0, x18 bl errata_neoverse_v1_1791573_wa diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 6f80d2d4f..3de013935 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -372,6 +372,10 @@ ERRATA_N1_1868343 ?=0 # exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround. ERRATA_N1_1946160 ?=0 +# Flag to apply erratum 1774420 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. +ERRATA_V1_1774420 ?=0 + # Flag to apply erratum 1791573 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1791573 ?=0 @@ -685,6 +689,10 @@ $(eval $(call add_define,ERRATA_N1_1868343)) $(eval $(call assert_boolean,ERRATA_N1_1946160)) $(eval $(call add_define,ERRATA_N1_1946160)) +# Process ERRATA_V1_1774420 flag +$(eval $(call assert_boolean,ERRATA_V1_1774420)) +$(eval $(call add_define,ERRATA_V1_1774420)) + # Process ERRATA_V1_1791573 flag $(eval $(call assert_boolean,ERRATA_V1_1791573)) $(eval $(call add_define,ERRATA_V1_1791573))