Browse Source
* changes: feat(fvp): allow SIMD context to be put in TZC DRAM docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag feat(fvp): add Cactus partition manifest for EL3 SPMC chore(simd): remove unused macros and utilities for FP feat(el3-spmc): support simd context management upon world switch feat(trusty): switch to simd_ctx_save/restore apis feat(pncd): switch to simd_ctx_save/restore apis feat(spm-mm): switch to simd_ctx_save/restore APIs feat(simd): add rules to rationalize simd ctxt mgmt feat(simd): introduce simd context helper APIs feat(simd): add routines to save, restore sve state feat(simd): add sve state to simd ctxt struct feat(simd): add data struct for simd ctxt managementpull/2005/merge
Manish V Badarkhe
3 months ago
committed by
TrustedFirmware Code Review
TrustedFirmware Code Review
18 changed files with 636 additions and 195 deletions
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. |
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* Copyright (c) 2022, Google LLC. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef SIMD_CTX_H |
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#define SIMD_CTX_H |
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'simd_context' |
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* structure at their correct offsets. |
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******************************************************************************/ |
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#if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS |
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#if CTX_INCLUDE_SVE_REGS |
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#define SIMD_VECTOR_LEN_BYTES (SVE_VECTOR_LEN / 8) /* Length of vector in bytes */ |
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#elif CTX_INCLUDE_FPREGS |
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#define SIMD_VECTOR_LEN_BYTES U(16) /* 128 bits fixed vector length for FPU */ |
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#endif /* CTX_INCLUDE_SVE_REGS */ |
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#define CTX_SIMD_VECTORS U(0) |
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/* there are 32 vector registers, each of size SIMD_VECTOR_LEN_BYTES */ |
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#define CTX_SIMD_FPSR (CTX_SIMD_VECTORS + (32 * SIMD_VECTOR_LEN_BYTES)) |
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#define CTX_SIMD_FPCR (CTX_SIMD_FPSR + 8) |
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#if CTX_INCLUDE_FPREGS && CTX_INCLUDE_AARCH32_REGS |
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#define CTX_SIMD_FPEXC32 (CTX_SIMD_FPCR + 8) |
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#define CTX_SIMD_PREDICATES (CTX_SIMD_FPEXC32 + 16) |
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#else |
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#define CTX_SIMD_PREDICATES (CTX_SIMD_FPCR + 8) |
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#endif /* CTX_INCLUDE_FPREGS && CTX_INCLUDE_AARCH32_REGS */ |
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/*
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* Each predicate register is 1/8th the size of a vector register and there are 16 |
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* predicate registers |
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*/ |
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#define CTX_SIMD_FFR (CTX_SIMD_PREDICATES + (16 * (SIMD_VECTOR_LEN_BYTES / 8))) |
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#ifndef __ASSEMBLER__ |
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#include <stdint.h> |
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#include <lib/cassert.h> |
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/*
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* Please don't change order of fields in this struct as that may violate |
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* alignment requirements and affect how assembly code accesses members of this |
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* struct. |
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*/ |
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typedef struct { |
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uint8_t vectors[32][SIMD_VECTOR_LEN_BYTES]; |
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uint8_t fpsr[8]; |
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uint8_t fpcr[8]; |
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#if CTX_INCLUDE_FPREGS && CTX_INCLUDE_AARCH32_REGS |
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/* 16 bytes to align to next 16 byte boundary when CTX_INCLUDE_SVE_REGS is 0 */ |
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uint8_t fpexc32_el2[16]; |
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#endif |
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#if CTX_INCLUDE_SVE_REGS |
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/* FFR and each of predicates is one-eigth of the SVE vector length */ |
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uint8_t predicates[16][SIMD_VECTOR_LEN_BYTES / 8]; |
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uint8_t ffr[SIMD_VECTOR_LEN_BYTES / 8]; |
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/* SMCCCv1.3 FID[16] hint bit state recorded on EL3 entry */ |
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bool hint; |
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#endif /* CTX_INCLUDE_SVE_REGS */ |
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} __aligned(16) simd_regs_t; |
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CASSERT(CTX_SIMD_VECTORS == __builtin_offsetof(simd_regs_t, vectors), |
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assert_vectors_mismatch); |
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CASSERT(CTX_SIMD_FPSR == __builtin_offsetof(simd_regs_t, fpsr), |
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assert_fpsr_mismatch); |
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CASSERT(CTX_SIMD_FPCR == __builtin_offsetof(simd_regs_t, fpcr), |
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assert_fpcr_mismatch); |
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#if CTX_INCLUDE_FPREGS && CTX_INCLUDE_AARCH32_REGS |
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CASSERT(CTX_SIMD_FPEXC32 == __builtin_offsetof(simd_regs_t, fpexc32_el2), |
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assert_fpex32_mismtatch); |
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#endif |
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#if CTX_INCLUDE_SVE_REGS |
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CASSERT(CTX_SIMD_PREDICATES == __builtin_offsetof(simd_regs_t, predicates), |
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assert_predicates_mismatch); |
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CASSERT(CTX_SIMD_FFR == __builtin_offsetof(simd_regs_t, ffr), |
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assert_ffr_mismatch); |
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#endif |
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void simd_ctx_save(uint32_t security_state, bool hint_sve); |
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void simd_ctx_restore(uint32_t security_state); |
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#endif /* __ASSEMBLER__ */ |
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#endif /* CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS */ |
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#endif /* SIMD_CTX_H */ |
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. |
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* Copyright (c) 2022, Google LLC. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <stdint.h> |
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#include <common/debug.h> |
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#include <lib/el3_runtime/aarch64/context.h> |
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#include <lib/el3_runtime/context_mgmt.h> |
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#include <lib/el3_runtime/cpu_data.h> |
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#include <lib/el3_runtime/simd_ctx.h> |
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#include <lib/extensions/sve.h> |
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#include <plat/common/platform.h> |
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#if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS |
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/* SIMD context managed for Secure and Normal Worlds. */ |
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#define SIMD_CTXT_COUNT 2 |
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#if SEPARATE_SIMD_SECTION |
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__section(".simd_context") |
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#else |
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__section(".bss.simd_context") |
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#endif |
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static simd_regs_t simd_context[SIMD_CTXT_COUNT][PLATFORM_CORE_COUNT]; |
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void simd_ctx_save(uint32_t security_state, bool hint_sve) |
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{ |
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simd_regs_t *regs; |
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if (security_state != NON_SECURE && security_state != SECURE) { |
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ERROR("Unsupported security state specified for SIMD context: %u\n", |
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security_state); |
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panic(); |
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} |
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regs = &simd_context[security_state][plat_my_core_pos()]; |
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#if CTX_INCLUDE_SVE_REGS |
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regs->hint = hint_sve; |
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if (hint_sve) { |
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/*
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* Hint bit denoting absence of SVE live state. Hence, only |
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* save FP context. |
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*/ |
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fpregs_context_save(regs); |
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} else { |
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sve_context_save(regs); |
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} |
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#elif CTX_INCLUDE_FPREGS |
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fpregs_context_save(regs); |
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#endif |
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} |
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void simd_ctx_restore(uint32_t security_state) |
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{ |
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simd_regs_t *regs; |
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if (security_state != NON_SECURE && security_state != SECURE) { |
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ERROR("Unsupported security state specified for SIMD context: %u\n", |
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security_state); |
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panic(); |
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} |
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regs = &simd_context[security_state][plat_my_core_pos()]; |
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#if CTX_INCLUDE_SVE_REGS |
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if (regs->hint) { |
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fpregs_context_restore(regs); |
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} else { |
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sve_context_restore(regs); |
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} |
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#elif CTX_INCLUDE_FPREGS |
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fpregs_context_restore(regs); |
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#endif |
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} |
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#endif /* CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS */ |
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@ -0,0 +1,28 @@ |
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/* |
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* Copyright (c) 2024, Arm Limited. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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* |
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* This file is a Partition Manifest (PM) for a minimal Secure Partition (SP) |
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* that will be consumed by EL3 SPMC. |
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* |
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*/ |
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/dts-v1/; |
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/ { |
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compatible = "arm,ffa-manifest-1.0"; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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/* Properties */ |
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ffa-version = <0x00010001>; /* 31:16 - Major, 15:0 - Minor */ |
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id = <0x8001>; |
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uuid = <0x1e67b5b4 0xe14f904a 0x13fb1fb8 0xcbdae1da>; |
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messaging-method = <3>; /* Direct messaging only */ |
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exception-level = <2>; /* S-EL1 */ |
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execution-state = <0>; /* AARCH64 */ |
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execution-ctx-count = <8>; |
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/* Boot protocol */ |
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gp-register-num = <0>; |
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}; |
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