github
/
arm-trusted-firmware
mirror of https://github.com/ARM-software/arm-trusted-firmware.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

feat(st): update STM32MP DT files 

This is an alignment with Linux DT files that have been merged in
stm32 tree [1], and will be in Linux 6.7.
The /omit-if-no-ref/ in overlay files are now removed, as already in
pinctrl files.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iab94b0ba7a4a0288ca53d1ae57ab590566967415
pull/1993/merge
Yann Gautier 1 year ago
parent
f8363a8e2c
commit
4c8e8ea772
20 changed files with 111 additions and 133 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 9
      fdts/stm32mp13-bl2.dtsi
  2. 8
      fdts/stm32mp13-pinctrl.dtsi
  3. 24
      fdts/stm32mp131.dtsi
  4. 29
      fdts/stm32mp15-bl2.dtsi
  5. 29
      fdts/stm32mp15-bl32.dtsi
  6. 61
      fdts/stm32mp15-pinctrl.dtsi
  7. 14
      fdts/stm32mp151.dtsi
  8. 6
      fdts/stm32mp151a-prtt1a.dts
  9. 8
      fdts/stm32mp157a-dk1.dts
  10. 5
      fdts/stm32mp157c-dk2.dts
  11. 10
      fdts/stm32mp157c-ed1.dts
  12. 16
      fdts/stm32mp157c-ev1.dts
  13. 5
      fdts/stm32mp15xx-dhcom-som.dtsi
  14. 5
      fdts/stm32mp15xx-dhcor-som.dtsi
  15. 6
      fdts/stm32mp15xx-dkx.dtsi
  16. 2
      fdts/stm32mp25-bl2.dtsi
  17. 1
      fdts/stm32mp25-pinctrl.dtsi
  18. 2
      fdts/stm32mp251.dtsi
  19. 2
      fdts/stm32mp257f-ev1.dts
  20. 2
      plat/st/stm32mp1/stm32mp1_def.h

9
fdts/stm32mp13-bl2.dtsi
View File

@ -3,15 +3,6 @@
* Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*/
/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &sdmmc1_b4_pins_a;
/omit-if-no-ref/ &sdmmc1_clk_pins_a;
/omit-if-no-ref/ &sdmmc2_b4_pins_a;
/omit-if-no-ref/ &sdmmc2_clk_pins_a;
/omit-if-no-ref/ &uart4_pins_a;
/omit-if-no-ref/ &uart8_pins_a;
/omit-if-no-ref/ &usart1_pins_a;
/ {
aliases {
#if !STM32MP_EMMC && !STM32MP_SDMMC

8
fdts/stm32mp13-pinctrl.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
/omit-if-no-ref/
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */
@ -16,6 +17,7 @@
};
};
/omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@ -29,6 +31,7 @@
};
};
/omit-if-no-ref/
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
@ -38,6 +41,7 @@
};
};
/omit-if-no-ref/
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
@ -51,6 +55,7 @@
};
};
/omit-if-no-ref/
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
@ -60,6 +65,7 @@
};
};
/omit-if-no-ref/
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
@ -73,6 +79,7 @@
};
};
/omit-if-no-ref/
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
@ -88,6 +95,7 @@
};
};
/omit-if-no-ref/
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */

24
fdts/stm32mp131.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/clock/stm32mp13-clks.h>
@ -276,23 +276,20 @@
};
fmc: memory-controller@58002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
<4 0 0x80000000 0x10000000>; /* NAND */
#address-cells = <2>;
#size-cells = <1>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
nand-controller@4,0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp1-fmc2-nfc";
reg = <4 0x00000000 0x1000>,
<4 0x08010000 0x1000>,
@ -300,6 +297,8 @@
<4 0x01000000 0x1000>,
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -341,7 +340,7 @@
status = "disabled";
};
usbh_ohci: usbh-ohci@5800c000 {
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
clocks = <&rcc USBH>;
@ -350,7 +349,7 @@
status = "disabled";
};
usbh_ehci: usbh-ehci@5800d000 {
usbh_ehci: usb@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&rcc USBH>;
@ -424,7 +423,7 @@
cfg0_otp: cfg0_otp@0 {
reg = <0x0 0x2>;
};
part_number_otp: part_number_otp@4 {
part_number_otp: part-number-otp@4 {
reg = <0x4 0x2>;
};
monotonic_otp: monotonic_otp@10 {
@ -470,7 +469,6 @@
ranges = <0 0x50002000 0x8400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;

29
fdts/stm32mp15-bl2.dtsi
View File

@ -3,37 +3,8 @@
* Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
*/
/omit-if-no-ref/ &fmc_pins_a;
/omit-if-no-ref/ &i2c2_pins_a;
/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &i2c6;
/omit-if-no-ref/ &qspi_bk1_pins_a;
/omit-if-no-ref/ &qspi_bk2_pins_a;
/omit-if-no-ref/ &qspi_clk_pins_a;
/omit-if-no-ref/ &sdmmc1_b4_pins_a;
/omit-if-no-ref/ &sdmmc1_dir_pins_a;
/omit-if-no-ref/ &sdmmc1_dir_pins_b;
/omit-if-no-ref/ &sdmmc2_b4_pins_a;
/omit-if-no-ref/ &sdmmc2_b4_pins_b;
/omit-if-no-ref/ &sdmmc2_d47_pins_a;
/omit-if-no-ref/ &sdmmc2_d47_pins_b;
/omit-if-no-ref/ &sdmmc2_d47_pins_c;
/omit-if-no-ref/ &sdmmc2_d47_pins_d;
/omit-if-no-ref/ &spi6;
/omit-if-no-ref/ &uart4_pins_a;
/omit-if-no-ref/ &uart4_pins_b;
/omit-if-no-ref/ &uart7_pins_a;
/omit-if-no-ref/ &uart7_pins_b;
/omit-if-no-ref/ &uart7_pins_c;
/omit-if-no-ref/ &uart8_pins_a;
/omit-if-no-ref/ &usart2_pins_a;
/omit-if-no-ref/ &usart2_pins_b;
/omit-if-no-ref/ &usart2_pins_c;
/omit-if-no-ref/ &usart3_pins_a;
/omit-if-no-ref/ &usart3_pins_b;
/omit-if-no-ref/ &usart3_pins_c;
/omit-if-no-ref/ &usbotg_fs_dp_dm_pins_a;
/omit-if-no-ref/ &usbotg_hs_pins_a;
/ {
#if !STM32MP_EMMC && !STM32MP_SDMMC

29
fdts/stm32mp15-bl32.dtsi
View File

@ -3,37 +3,8 @@
* Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
*/
/omit-if-no-ref/ &fmc_pins_a;
/omit-if-no-ref/ &i2c2_pins_a;
/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &i2c6;
/omit-if-no-ref/ &qspi_bk1_pins_a;
/omit-if-no-ref/ &qspi_bk2_pins_a;
/omit-if-no-ref/ &qspi_clk_pins_a;
/omit-if-no-ref/ &sdmmc1_b4_pins_a;
/omit-if-no-ref/ &sdmmc1_dir_pins_a;
/omit-if-no-ref/ &sdmmc1_dir_pins_b;
/omit-if-no-ref/ &sdmmc2_b4_pins_a;
/omit-if-no-ref/ &sdmmc2_b4_pins_b;
/omit-if-no-ref/ &sdmmc2_d47_pins_a;
/omit-if-no-ref/ &sdmmc2_d47_pins_b;
/omit-if-no-ref/ &sdmmc2_d47_pins_c;
/omit-if-no-ref/ &sdmmc2_d47_pins_d;
/omit-if-no-ref/ &spi6;
/omit-if-no-ref/ &uart4_pins_a;
/omit-if-no-ref/ &uart4_pins_b;
/omit-if-no-ref/ &uart7_pins_a;
/omit-if-no-ref/ &uart7_pins_b;
/omit-if-no-ref/ &uart7_pins_c;
/omit-if-no-ref/ &uart8_pins_a;
/omit-if-no-ref/ &usart2_pins_a;
/omit-if-no-ref/ &usart2_pins_b;
/omit-if-no-ref/ &usart2_pins_c;
/omit-if-no-ref/ &usart3_pins_a;
/omit-if-no-ref/ &usart3_pins_b;
/omit-if-no-ref/ &usart3_pins_c;
/omit-if-no-ref/ &usbotg_fs_dp_dm_pins_a;
/omit-if-no-ref/ &usbotg_hs_pins_a;
/ {
aliases {

61
fdts/stm32mp15-pinctrl.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
/omit-if-no-ref/
fmc_pins_a: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@ -31,6 +32,7 @@
};
};
/omit-if-no-ref/
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
@ -41,6 +43,7 @@
};
};
/omit-if-no-ref/
qspi_clk_pins_a: qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
@ -50,8 +53,9 @@
};
};
/omit-if-no-ref/
qspi_bk1_pins_a: qspi-bk1-0 {
pins1 {
pins {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
@ -60,16 +64,11 @@
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
};
/omit-if-no-ref/
qspi_bk2_pins_a: qspi-bk2-0 {
pins1 {
pins {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
@ -78,7 +77,21 @@
drive-push-pull;
slew-rate = <1>;
};
pins2 {
};
/omit-if-no-ref/
qspi_cs1_pins_a: qspi-cs1-0 {
pins {
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
};
/omit-if-no-ref/
qspi_cs2_pins_a: qspi-cs2-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
@ -86,6 +99,7 @@
};
};
/omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@ -105,6 +119,7 @@
};
};
/omit-if-no-ref/
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@ -120,6 +135,7 @@
};
};
/omit-if-no-ref/
sdmmc1_dir_pins_b: sdmmc1-dir-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@ -129,12 +145,13 @@
drive-push-pull;
bias-pull-up;
};
pins2{
pins2 {
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
bias-pull-up;
};
};
/omit-if-no-ref/
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
@ -154,6 +171,7 @@
};
};
/omit-if-no-ref/
sdmmc2_b4_pins_b: sdmmc2-b4-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
@ -173,6 +191,7 @@
};
};
/omit-if-no-ref/
sdmmc2_d47_pins_a: sdmmc2-d47-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@ -185,6 +204,7 @@
};
};
/omit-if-no-ref/
sdmmc2_d47_pins_b: sdmmc2-d47-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@ -197,6 +217,7 @@
};
};
/omit-if-no-ref/
sdmmc2_d47_pins_c: sdmmc2-d47-2 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@ -209,6 +230,7 @@
};
};
/omit-if-no-ref/
sdmmc2_d47_pins_d: sdmmc2-d47-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@ -218,6 +240,7 @@
};
};
/omit-if-no-ref/
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
@ -231,6 +254,7 @@
};
};
/omit-if-no-ref/
uart4_pins_b: uart4-1 {
pins1 {
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
@ -244,6 +268,7 @@
};
};
/omit-if-no-ref/
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
@ -259,6 +284,7 @@
};
};
/omit-if-no-ref/
uart7_pins_b: uart7-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
@ -272,6 +298,7 @@
};
};
/omit-if-no-ref/
uart7_pins_c: uart7-2 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
@ -281,10 +308,11 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
bias-disable;
bias-pull-up;
};
};
/omit-if-no-ref/
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
@ -298,6 +326,7 @@
};
};
/omit-if-no-ref/
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@ -313,6 +342,7 @@
};
};
/omit-if-no-ref/
usart2_pins_b: usart2-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@ -328,13 +358,14 @@
};
};
/omit-if-no-ref/
usart2_pins_c: usart2-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@ -343,6 +374,7 @@
};
};
/omit-if-no-ref/
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
@ -356,6 +388,7 @@
};
};
/omit-if-no-ref/
usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@ -371,6 +404,7 @@
};
};
/omit-if-no-ref/
usart3_pins_c: usart3-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@ -386,12 +420,14 @@
};
};
/omit-if-no-ref/
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};
};
/omit-if-no-ref/
usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
@ -401,6 +437,7 @@
};
&pinctrl_z {
/omit-if-no-ref/
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */

14
fdts/stm32mp151.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -324,9 +324,8 @@
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
@ -339,9 +338,8 @@
sdmmc2: mmc@58007000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
@ -463,7 +461,7 @@
cfg0_otp: cfg0_otp@0 {
reg = <0x0 0x1>;
};
part_number_otp: part_number_otp@4 {
part_number_otp: part-number-otp@4 {
reg = <0x4 0x1>;
};
monotonic_otp: monotonic_otp@10 {
@ -523,7 +521,7 @@
};
tamp: tamp@5c00a000 {
compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd";
compatible = "st,stm32-tamp", "syscon", "simple-mfd";
reg = <0x5c00a000 0x400>;
secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc RTCAPB>;
@ -540,7 +538,6 @@
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
@ -669,7 +666,6 @@
#size-cells = <1>;
compatible = "st,stm32mp157-z-pinctrl";
ranges = <0 0x54004000 0x400>;
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;

6
fdts/stm32mp151a-prtt1a.dts
View File

@ -39,7 +39,9 @@
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-0 = <&qspi_clk_pins_a
&qspi_bk1_pins_a
&qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
@ -56,7 +58,7 @@
};
&qspi_bk1_pins_a {
pins1 {
pins {
bias-pull-up;
drive-push-pull;
slew-rate = <1>;

8
fdts/stm32mp157a-dk1.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Copyright (C) 2019-2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
@ -15,12 +15,6 @@
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};

5
fdts/stm32mp157c-dk2.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Copyright (C) 2019-2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
@ -17,9 +17,6 @@
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
serial3 = &usart2;
};

10
fdts/stm32mp157c-ed1.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
/dts-v1/;
@ -16,6 +16,10 @@
model = "STMicroelectronics STM32MP157C eval daughter";
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
aliases {
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
@ -24,10 +28,6 @@
device_type = "memory";
reg = <0xC0000000 0x40000000>;
};
aliases {
serial0 = &uart4;
};
};
&bsec {

16
fdts/stm32mp157c-ev1.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
/dts-v1/;
@ -11,13 +11,13 @@
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial1 = &usart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&fmc {
@ -39,13 +39,15 @@
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-0 = <&qspi_clk_pins_a
&qspi_bk1_pins_a
&qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: mx66l51235l@0 {
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;

5
fdts/stm32mp15xx-dhcom-som.dtsi
View File

@ -2,6 +2,7 @@
/*
* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
* Copyright (C) 2022 DH electronics GmbH
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp15-pinctrl.dtsi"
@ -169,7 +170,9 @@
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-0 = <&qspi_clk_pins_a
&qspi_bk1_pins_a
&qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;

5
fdts/stm32mp15xx-dhcor-som.dtsi
View File

@ -4,6 +4,7 @@
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
* Copyright (C) 2022 DH electronics GmbH
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp15-pinctrl.dtsi"
@ -164,7 +165,9 @@
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-0 = <&qspi_clk_pins_a
&qspi_bk1_pins_a
&qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
#address-cells = <1>;
#size-cells = <0>;

6
fdts/stm32mp15xx-dkx.dtsi
View File

@ -8,6 +8,12 @@
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;

2
fdts/stm32mp25-bl2.dtsi
View File

@ -2,5 +2,3 @@
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
/omit-if-no-ref/ &usart2_pins_a;

1
fdts/stm32mp25-pinctrl.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
/omit-if-no-ref/
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */

2
fdts/stm32mp251.dtsi
View File

@ -67,7 +67,7 @@
<0x0 0x4ac60000 0x0 0x2000>;
};
timer: timer {
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

2
fdts/stm32mp257f-ev1.dts
View File

@ -25,7 +25,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x00000000>;
reg = <0x0 0x80000000 0x1 0x0>;
};
};

2
plat/st/stm32mp1/stm32mp1_def.h
View File

@ -427,7 +427,7 @@ enum ddr_type {
/* OTP labels */
#define CFG0_OTP "cfg0_otp"
#define PART_NUMBER_OTP "part_number_otp"
#define PART_NUMBER_OTP "part-number-otp"
#if STM32MP15
#define PACKAGE_OTP "package_otp"
#endif

Write Preview
Loading…
Cancel
Save