diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 60290357a..71208a8fd 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -474,6 +474,25 @@ For Cortex-X2, the following errata build flags are defined : Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the CPU, it is fixed in r2p1. +For Cortex-A510, the following errata build flags are defined : + +- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to + Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is + fixed in r0p1. + +- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to + Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, + r0p2, r0p3 and r1p0, it is fixed in r1p1. + +- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to + Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and + r0p2, it is fixed in r0p3. + +- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to + Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed + in r0p3. The issue is also present in r0p0 and r0p1 but there is no + workaround for those revisions. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h index 6a4cfdfe3..fcb821fb4 100644 --- a/include/lib/cpus/aarch64/cortex_a510.h +++ b/include/lib/cpus/aarch64/cortex_a510.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,8 @@ * CPU Extended Control register specific definitions ******************************************************************************/ #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) /******************************************************************************* * CPU Power Control register specific definitions @@ -20,4 +22,14 @@ #define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +/******************************************************************************* + * Complex auxiliary control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 + +/******************************************************************************* + * Auxiliary control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 + #endif /* CORTEX_A510_H */ diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index 33103228a..c288cb23d 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,14 +13,146 @@ /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 -#error "Cortex A510 must be compiled with HW_ASSISTED_COHERENCY enabled" +#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif /* 64-bit only core */ #if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif + /* -------------------------------------------------- + * Errata Workaround for Cortex-A510 Errata #1922240. + * This applies only to revision r0p0 (fixed in r0p1) + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x17 + * -------------------------------------------------- + */ +func errata_cortex_a510_1922240_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1922240 + cbz x0, 1f + + /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ + mrs x0, CORTEX_A510_CMPXACTLR_EL1 + mov x1, #3 + bfi x0, x1, #10, #2 + msr CORTEX_A510_CMPXACTLR_EL1, x0 + +1: + ret x17 +endfunc errata_cortex_a510_1922240_wa + +func check_errata_1922240 + /* Applies to r0p0 only */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_1922240 + + /* -------------------------------------------------- + * Errata Workaround for Cortex-A510 Errata #2288014. + * This applies only to revisions r0p0, r0p1, r0p2, + * r0p3 and r1p0. (fixed in r1p1) + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x17 + * -------------------------------------------------- + */ +func errata_cortex_a510_2288014_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2288014 + cbz x0, 1f + + /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ + mrs x0, CORTEX_A510_CPUACTLR_EL1 + mov x1, #1 + bfi x0, x1, #18, #1 + msr CORTEX_A510_CPUACTLR_EL1, x0 + +1: + ret x17 +endfunc errata_cortex_a510_2288014_wa + +func check_errata_2288014 + /* Applies to r1p0 and below */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_2288014 + + /* -------------------------------------------------- + * Errata Workaround for Cortex-A510 Errata #2042739. + * This applies only to revisions r0p0, r0p1 and r0p2. + * (fixed in r0p3) + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x17 + * -------------------------------------------------- + */ +func errata_cortex_a510_2042739_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2042739 + cbz x0, 1f + + /* Apply the workaround by disabling ReadPreferUnique. */ + mrs x0, CORTEX_A510_CPUECTLR_EL1 + mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE + bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1 + msr CORTEX_A510_CPUECTLR_EL1, x0 + +1: + ret x17 +endfunc errata_cortex_a510_2042739_wa + +func check_errata_2042739 + /* Applies to revisions r0p0 - r0p2 */ + mov x1, #0x02 + b cpu_rev_var_ls +endfunc check_errata_2042739 + + /* -------------------------------------------------- + * Errata Workaround for Cortex-A510 Errata #2041909. + * This applies only to revision r0p2 and it is fixed in + * r0p3. The issue is also present in r0p0 and r0p1 but + * there is no workaround in those revisions. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x2, x17 + * -------------------------------------------------- + */ +func errata_cortex_a510_2041909_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2041909 + cbz x0, 1f + + /* Apply workaround */ + mov x0, xzr + msr S3_6_C15_C4_0, x0 + isb + + mov x0, #0x8500000 + msr S3_6_C15_C4_2, x0 + + mov x0, #0x1F700000 + movk x0, #0x8, lsl #32 + msr S3_6_C15_C4_3, x0 + + mov x0, #0x3F1 + movk x0, #0x110, lsl #16 + msr S3_6_C15_C4_1, x0 + isb + +1: + ret x17 +endfunc errata_cortex_a510_2041909_wa + +func check_errata_2041909 + /* Applies only to revision r0p2 */ + mov x1, #0x02 + mov x2, #0x02 + b cpu_rev_var_range +endfunc check_errata_2041909 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -38,19 +170,61 @@ func cortex_a510_core_pwr_dwn endfunc cortex_a510_core_pwr_dwn /* - * Errata printing function for Cortex A510. Must follow AAPCS. + * Errata printing function for Cortex-A510. Must follow AAPCS. */ #if REPORT_ERRATA func cortex_a510_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A510_1922240, cortex_a510, 1922240 + report_errata ERRATA_A510_2288014, cortex_a510, 2288014 + report_errata ERRATA_A510_2042739, cortex_a510, 2042739 + report_errata ERRATA_A510_2041909, cortex_a510, 2041909 + + ldp x8, x30, [sp], #16 ret endfunc cortex_a510_errata_report #endif func cortex_a510_reset_func + mov x19, x30 + /* Disable speculative loads */ msr SSBS, xzr isb - ret + + /* Get the CPU revision and stash it in x18. */ + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A510_1922240 + mov x0, x18 + bl errata_cortex_a510_1922240_wa +#endif + +#if ERRATA_A510_2288014 + mov x0, x18 + bl errata_cortex_a510_2288014_wa +#endif + +#if ERRATA_A510_2042739 + mov x0, x18 + bl errata_cortex_a510_2042739_wa +#endif + +#if ERRATA_A510_2041909 + mov x0, x18 + bl errata_cortex_a510_2041909_wa +#endif + + ret x19 endfunc cortex_a510_reset_func /* --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index e02aa019c..107753e0f 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -7,27 +7,27 @@ # Cortex A57 specific optimisation to skip L1 cache flush when # cluster is powered down. -SKIP_A57_L1_FLUSH_PWR_DWN ?=0 +SKIP_A57_L1_FLUSH_PWR_DWN ?=0 # Flag to disable the cache non-temporal hint. # It is enabled by default. -A53_DISABLE_NON_TEMPORAL_HINT ?=1 +A53_DISABLE_NON_TEMPORAL_HINT ?=1 # Flag to disable the cache non-temporal hint. # It is enabled by default. -A57_DISABLE_NON_TEMPORAL_HINT ?=1 +A57_DISABLE_NON_TEMPORAL_HINT ?=1 # Flag to enable higher performance non-cacheable load forwarding. # It is disabled by default. A57_ENABLE_NONCACHEABLE_LOAD_FWD ?= 0 -WORKAROUND_CVE_2017_5715 ?=1 -WORKAROUND_CVE_2018_3639 ?=1 +WORKAROUND_CVE_2017_5715 ?=1 +WORKAROUND_CVE_2018_3639 ?=1 DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0 # Flags to indicate internal or external Last level cache # By default internal -NEOVERSE_Nx_EXTERNAL_LLC ?=0 +NEOVERSE_Nx_EXTERNAL_LLC ?=0 # Process A57_ENABLE_NONCACHEABLE_LOAD_FWD flag $(eval $(call assert_boolean,A57_ENABLE_NONCACHEABLE_LOAD_FWD)) @@ -60,9 +60,9 @@ $(eval $(call assert_boolean,NEOVERSE_Nx_EXTERNAL_LLC)) $(eval $(call add_define,NEOVERSE_Nx_EXTERNAL_LLC)) ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0) - ifeq (${WORKAROUND_CVE_2018_3639},0) - $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1") - endif + ifeq (${WORKAROUND_CVE_2018_3639},0) + $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1") + endif endif # CPU Errata Build flags. @@ -108,7 +108,7 @@ ERRATA_A53_826319 ?=0 # only to revision <= r0p2 of the Cortex A53 cpu. ERRATA_A53_827319 ?=0 -# Flag to apply erratum 835769 workaround at compile and link time. This +# Flag to apply erratum 835769 workaround at compile and link time. This # erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this # workaround can lead the linker to create "*.stub" sections. ERRATA_A53_835769 ?=0 @@ -170,11 +170,11 @@ ERRATA_A57_806969 ?=0 # only to revision r0p0 of the Cortex A57 cpu. ERRATA_A57_813419 ?=0 -# Flag to apply erratum 813420 workaround during reset. This erratum applies +# Flag to apply erratum 813420 workaround during reset. This erratum applies # only to revision r0p0 of the Cortex A57 cpu. ERRATA_A57_813420 ?=0 -# Flag to apply erratum 814670 workaround during reset. This erratum applies +# Flag to apply erratum 814670 workaround during reset. This erratum applies # only to revision r0p0 of the Cortex A57 cpu. ERRATA_A57_814670 ?=0 @@ -307,7 +307,7 @@ ERRATA_A78_1688305 ?=0 ERRATA_A78_1941498 ?=0 # Flag to apply erratum 1951500 workaround during reset. This erratum applies -# to revisions r1p0 and r1p1 of the A78 cpu. The issue is present in r0p0 as +# to revisions r1p0 and r1p1 of the A78 cpu. The issue is present in r0p0 as # well but there is no workaround for that revision. ERRATA_A78_1951500 ?=0 @@ -317,11 +317,11 @@ ERRATA_A78_1821534 ?=0 # Flag to apply erratum 1952683 workaround during reset. This erratum applies # to revision r0p0 of the A78 cpu and was fixed in the revision r1p0. -ERRATA_A78_1952683 ?=0 +ERRATA_A78_1952683 ?=0 # Flag to apply erratum 2132060 workaround during reset. This erratum applies # to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open. -ERRATA_A78_2132060 ?=0 +ERRATA_A78_2132060 ?=0 # Flag to apply erratum 2242635 workaround during reset. This erratum applies # to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is @@ -389,7 +389,7 @@ ERRATA_N1_1542419 ?=0 ERRATA_N1_1868343 ?=0 # Flag to apply erratum 1946160 workaround during reset. This erratum applies -# to revisions r3p0, r3p1, r4p0, and r4p1 of the Neoverse N1 cpu. The issue +# to revisions r3p0, r3p1, r4p0, and r4p1 of the Neoverse N1 cpu. The issue # exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround. ERRATA_N1_1946160 ?=0 @@ -397,19 +397,19 @@ ERRATA_N1_1946160 ?=0 # to revisions r0p0 of the Neoverse-N2 cpu, it is still open. ERRATA_N2_2002655 ?=0 -# Flag to apply erratum 1774420 workaround during reset. This erratum applies +# Flag to apply erratum 1774420 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1774420 ?=0 -# Flag to apply erratum 1791573 workaround during reset. This erratum applies +# Flag to apply erratum 1791573 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1791573 ?=0 -# Flag to apply erratum 1852267 workaround during reset. This erratum applies +# Flag to apply erratum 1852267 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1852267 ?=0 -# Flag to apply erratum 1925756 workaround during reset. This needs to be +# Flag to apply erratum 1925756 workaround during reset. This needs to be # enabled for r0p0, r1p0, and r1p1 of the Neoverse V1 core, it is still open. ERRATA_V1_1925756 ?=0 @@ -418,7 +418,7 @@ ERRATA_V1_1925756 ?=0 ERRATA_V1_1940577 ?=0 # Flag to apply erratum 1966096 workaround during reset. This erratum applies -# to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open. This issue +# to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open. This issue # exists in r0p0 as well but there is no workaround for that revision. ERRATA_V1_1966096 ?=0 @@ -451,6 +451,22 @@ ERRATA_A710_2083908 ?=0 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2058056 ?=0 +# Flag to apply erratum 2055002 workaround during reset. This erratum applies +# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_2055002 ?=0 + +# Flag to apply erratum 2017096 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_2017096 ?=0 + +# Flag to apply erratum 2267065 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. +ERRATA_A710_2267065 ?=0 + +# Flag to apply erratum 2136059 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. +ERRATA_A710_2136059 ?=0 + # Flag to apply erratum 2067956 workaround during reset. This erratum applies # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2067956 ?=0 @@ -487,22 +503,6 @@ ERRATA_N2_2242400 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2280757 ?=0 -# Flag to apply erratum 2055002 workaround during reset. This erratum applies -# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. -ERRATA_A710_2055002 ?=0 - -# Flag to apply erratum 2017096 workaround during reset. This erratum applies -# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. -ERRATA_A710_2017096 ?=0 - -# Flag to apply erratum 2267065 workaround during reset. This erratum applies -# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. -ERRATA_A710_2267065 ?=0 - -# Flag to apply erratum 2136059 workaround during reset. This erratum applies -# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. -ERRATA_A710_2136059 ?=0 - # Flag to apply erratum 2002765 workaround during reset. This erratum applies # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open. ERRATA_X2_2002765 ?=0 @@ -530,6 +530,24 @@ ERRATA_X2_2081180 ?=0 # r2p1. ERRATA_X2_2216384 ?=0 +# Flag to apply erratum 1922240 workaround during reset. This erratum applies +# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. +ERRATA_A510_1922240 ?=0 + +# Flag to apply erratum 2288014 workaround during reset. This erratum applies +# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0 of the Cortex-A510 cpu and is +# fixed in r1p1. +ERRATA_A510_2288014 ?=0 + +# Flag to apply erratum 2042739 workaround during reset. This erratum applies +# to revisions r0p0, r0p1 and r0p2 of the Cortex-A510 cpu and is fixed in r0p3. +ERRATA_A510_2042739 ?=0 + +# Flag to apply erratum 2041909 workaround during reset. This erratum applies +# to revision r0p2 of the Cortex-A510 cpu and is fixed in r0p3. The issue is +# present in r0p0 and r0p1 but there is no workaround for those revisions. +ERRATA_A510_2041909 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -911,6 +929,22 @@ $(eval $(call add_define,ERRATA_A710_2083908)) $(eval $(call assert_boolean,ERRATA_A710_2058056)) $(eval $(call add_define,ERRATA_A710_2058056)) +# Process ERRATA_A710_2055002 flag +$(eval $(call assert_boolean,ERRATA_A710_2055002)) +$(eval $(call add_define,ERRATA_A710_2055002)) + +# Process ERRATA_A710_2017096 flag +$(eval $(call assert_boolean,ERRATA_A710_2017096)) +$(eval $(call add_define,ERRATA_A710_2017096)) + +# Process ERRATA_A710_2267065 flag +$(eval $(call assert_boolean,ERRATA_A710_2267065)) +$(eval $(call add_define,ERRATA_A710_2267065)) + +# Process ERRATA_A710_2136059 flag +$(eval $(call assert_boolean,ERRATA_A710_2136059)) +$(eval $(call add_define,ERRATA_A710_2136059)) + # Process ERRATA_N2_2067956 flag $(eval $(call assert_boolean,ERRATA_N2_2067956)) $(eval $(call add_define,ERRATA_N2_2067956)) @@ -947,22 +981,6 @@ $(eval $(call add_define,ERRATA_N2_2242400)) $(eval $(call assert_boolean,ERRATA_N2_2280757)) $(eval $(call add_define,ERRATA_N2_2280757)) -# Process ERRATA_A710_2055002 flag -$(eval $(call assert_boolean,ERRATA_A710_2055002)) -$(eval $(call add_define,ERRATA_A710_2055002)) - -# Process ERRATA_A710_2017096 flag -$(eval $(call assert_boolean,ERRATA_A710_2017096)) -$(eval $(call add_define,ERRATA_A710_2017096)) - -# Process ERRATA_A710_2267065 flag -$(eval $(call assert_boolean,ERRATA_A710_2267065)) -$(eval $(call add_define,ERRATA_A710_2267065)) - -# Process ERRATA_A710_2136059 flag -$(eval $(call assert_boolean,ERRATA_A710_2136059)) -$(eval $(call add_define,ERRATA_A710_2136059)) - # Process ERRATA_X2_2002765 flag $(eval $(call assert_boolean,ERRATA_X2_2002765)) $(eval $(call add_define,ERRATA_X2_2002765)) @@ -987,6 +1005,22 @@ $(eval $(call add_define,ERRATA_X2_2081180)) $(eval $(call assert_boolean,ERRATA_X2_2216384)) $(eval $(call add_define,ERRATA_X2_2216384)) +# Process ERRATA_A510_1922240 flag +$(eval $(call assert_boolean,ERRATA_A510_1922240)) +$(eval $(call add_define,ERRATA_A510_1922240)) + +# Process ERRATA_A510_2288014 flag +$(eval $(call assert_boolean,ERRATA_A510_2288014)) +$(eval $(call add_define,ERRATA_A510_2288014)) + +# Process ERRATA_A510_2042739 flag +$(eval $(call assert_boolean,ERRATA_A510_2042739)) +$(eval $(call add_define,ERRATA_A510_2042739)) + +# Process ERRATA_A510_2041909 flag +$(eval $(call assert_boolean,ERRATA_A510_2041909)) +$(eval $(call add_define,ERRATA_A510_2041909)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953))