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Merge pull request #130 from athoelke/at/inline-asm-sysreg-v2 

Make system register functions inline assembly v2
pull/136/head
danh-arm 11 years ago
parent
3934d1a6cc 5c3272a717
commit
5c633bdff3
10 changed files with 249 additions and 1371 deletions
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  1. 1
      Makefile
  2. 85
      drivers/arm/gic/aarch64/gic_v3_sysregs.S
  3. 8
      include/drivers/arm/gic_v3.h
  4. 10
      include/lib/aarch64/arch.h
  5. 416
      include/lib/aarch64/arch_helpers.h
  6. 48
      lib/aarch64/cache_helpers.S
  7. 195
      lib/aarch64/misc_helpers.S
  8. 782
      lib/aarch64/sysreg_helpers.S
  9. 73
      lib/aarch64/tlb_helpers.S
  10. 2
      plat/fvp/platform.mk

1
Makefile
View File

@ -75,7 +75,6 @@ BL_COMMON_SOURCES := common/bl_common.c \
common/debug.c \
lib/aarch64/cache_helpers.S \
lib/aarch64/misc_helpers.S \
lib/aarch64/tlb_helpers.S \
lib/aarch64/xlat_helpers.c \
lib/stdlib/std.c \
lib/io_storage.c \

85
drivers/arm/gic/aarch64/gic_v3_sysregs.S
View File

@ -1,85 +0,0 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <asm_macros.S>
.globl read_icc_sre_el1
.globl read_icc_sre_el2
.globl read_icc_sre_el3
.globl write_icc_sre_el1
.globl write_icc_sre_el2
.globl write_icc_sre_el3
.globl write_icc_pmr_el1
/*
* Register definitions used by GCC for GICv3 access.
* These are defined by ARMCC, so keep them in the GCC specific code for now.
*/
#define ICC_SRE_EL1 S3_0_C12_C12_5
#define ICC_SRE_EL2 S3_4_C12_C9_5
#define ICC_SRE_EL3 S3_6_C12_C12_5
#define ICC_CTLR_EL1 S3_0_C12_C12_4
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_PMR_EL1 S3_0_C4_C6_0
func read_icc_sre_el1
mrs x0, ICC_SRE_EL1
ret
func read_icc_sre_el2
mrs x0, ICC_SRE_EL2
ret
func read_icc_sre_el3
mrs x0, ICC_SRE_EL3
ret
func write_icc_sre_el1
msr ICC_SRE_EL1, x0
ret
func write_icc_sre_el2
msr ICC_SRE_EL2, x0
ret
func write_icc_sre_el3
msr ICC_SRE_EL3, x0
ret
func write_icc_pmr_el1
msr ICC_PMR_EL1, x0
ret

8
include/drivers/arm/gic_v3.h
View File

@ -68,14 +68,6 @@
******************************************************************************/
uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr);
unsigned int read_icc_sre_el1(void);
unsigned int read_icc_sre_el2(void);
unsigned int read_icc_sre_el3(void);
void write_icc_sre_el1(unsigned int);
void write_icc_sre_el2(unsigned int);
void write_icc_sre_el3(unsigned int);
void write_icc_pmr_el1(unsigned int);
/*******************************************************************************
* GIC Redistributor interface accessors
******************************************************************************/

10
include/lib/aarch64/arch.h
View File

@ -64,6 +64,16 @@
/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
#define FIRST_MPIDR 0
/*******************************************************************************
* Definitions for CPU system register interface to GICv3
******************************************************************************/
#define ICC_SRE_EL1 S3_0_C12_C12_5
#define ICC_SRE_EL2 S3_4_C12_C9_5
#define ICC_SRE_EL3 S3_6_C12_C12_5
#define ICC_CTLR_EL1 S3_0_C12_C12_4
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_PMR_EL1 S3_0_C4_C6_0
/*******************************************************************************
* Implementation defined sysreg encodings
******************************************************************************/

416
include/lib/aarch64/arch_helpers.h
View File

@ -31,52 +31,115 @@
#ifndef __ARCH_HELPERS_H__
#define __ARCH_HELPERS_H__
#include <cdefs.h> /* For __dead2 */
#include <arch.h> /* for additional register definitions */
#include <cdefs.h> /* For __dead2 */
#include <stdint.h>
/**********************************************************************
* Macros which create inline functions to read or write CPU system
* registers
*********************************************************************/
#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
static inline uint64_t read_ ## _name(void) \
{ \
uint64_t v; \
__asm__ ("mrs %0, " #_reg_name : "=r" (v)); \
return v; \
}
#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
static inline void write_ ## _name(uint64_t v) \
{ \
__asm__ ("msr " #_reg_name ", %0" : : "r" (v)); \
}
#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
static inline void write_ ## _name(const uint64_t v) \
{ \
__asm__ ("msr " #_reg_name ", %0" : : "i" (v)); \
}
/* Define read function for system register */
#define DEFINE_SYSREG_READ_FUNC(_name) \
_DEFINE_SYSREG_READ_FUNC(_name, _name)
/* Define read & write function for system register */
#define DEFINE_SYSREG_RW_FUNCS(_name) \
_DEFINE_SYSREG_READ_FUNC(_name, _name) \
_DEFINE_SYSREG_WRITE_FUNC(_name, _name)
/* Define read & write function for renamed system register */
#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
_DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
_DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
/* Define write function for special system registers */
#define DEFINE_SYSREG_WRITE_CONST_FUNC(_name) \
_DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _name)
/**********************************************************************
* Macros to create inline functions for system instructions
*********************************************************************/
/* Define function for simple system instruction */
#define DEFINE_SYSOP_FUNC(_op) \
static inline void _op() \
{ \
__asm__ (#_op); \
}
/* Define function for system instruction with type specifier */
#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
static inline void _op ## _type() \
{ \
__asm__ (#_op " " #_type); \
}
/* Define function for system instruction with register parameter */
#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
static inline void _op ## _type(uint64_t v) \
{ \
__asm__ (#_op " " #_type ", %0" : : "r" (v)); \
}
/*******************************************************************************
* Aarch64 translation tables manipulation helper prototypes
******************************************************************************/
unsigned long create_table_desc(unsigned long *next_table_ptr);
unsigned long create_block_desc(unsigned long desc,
unsigned long addr,
unsigned int level);
unsigned long create_device_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
unsigned long create_romem_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
unsigned long create_rwmem_block(unsigned long output_addr,
unsigned int level,
unsigned int ns);
******************************************************************************/
uint64_t create_table_desc(uint64_t *next_table_ptr);
uint64_t create_block_desc(uint64_t desc, uint64_t addr, uint32_t level);
uint64_t create_device_block(uint64_t output_addr, uint32_t level, uint32_t ns);
uint64_t create_romem_block(uint64_t output_addr, uint32_t level, uint32_t ns);
uint64_t create_rwmem_block(uint64_t output_addr, uint32_t level, uint32_t ns);
/*******************************************************************************
* TLB maintenance accessor prototypes
******************************************************************************/
void tlbialle1(void);
void tlbialle1is(void);
void tlbialle2(void);
void tlbialle2is(void);
void tlbialle3(void);
void tlbialle3is(void);
void tlbivmalle1(void);
DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
/*******************************************************************************
* Cache maintenance accessor prototypes
******************************************************************************/
void dcisw(unsigned long);
void dccisw(unsigned long);
void dccsw(unsigned long);
void dccvac(unsigned long);
void dcivac(unsigned long);
void dccivac(unsigned long);
void dccvau(unsigned long);
void dczva(unsigned long);
void flush_dcache_range(unsigned long, unsigned long);
void inv_dcache_range(unsigned long, unsigned long);
void dcsw_op_louis(unsigned int);
void dcsw_op_all(unsigned int);
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
void flush_dcache_range(uint64_t, uint64_t);
void inv_dcache_range(uint64_t, uint64_t);
void dcsw_op_louis(uint32_t);
void dcsw_op_all(uint32_t);
void disable_mmu_el3(void);
void disable_mmu_icache_el3(void);
@ -84,202 +147,159 @@ void disable_mmu_icache_el3(void);
/*******************************************************************************
* Misc. accessor prototypes
******************************************************************************/
void enable_irq(void);
void enable_fiq(void);
void enable_serror(void);
void enable_debug_exceptions(void);
void disable_irq(void);
void disable_fiq(void);
void disable_serror(void);
void disable_debug_exceptions(void);
unsigned long read_id_pfr1_el1(void);
unsigned long read_id_aa64pfr0_el1(void);
unsigned long read_current_el(void);
unsigned long read_daif(void);
unsigned long read_spsr_el1(void);
unsigned long read_spsr_el2(void);
unsigned long read_spsr_el3(void);
unsigned long read_elr_el1(void);
unsigned long read_elr_el2(void);
unsigned long read_elr_el3(void);
void write_daif(unsigned long);
void write_spsr_el1(unsigned long);
void write_spsr_el2(unsigned long);
void write_spsr_el3(unsigned long);
void write_elr_el1(unsigned long);
void write_elr_el2(unsigned long);
void write_elr_el3(unsigned long);
void wfi(void);
void wfe(void);
void rfe(void);
void sev(void);
void dsb(void);
void isb(void);
unsigned int get_afflvl_shift(unsigned int);
unsigned int mpidr_mask_lower_afflvls(unsigned long, unsigned int);
void __dead2 eret(unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long);
void __dead2 smc(unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long);
DEFINE_SYSREG_WRITE_CONST_FUNC(daifset)
DEFINE_SYSREG_WRITE_CONST_FUNC(daifclr)
#define enable_irq() write_daifclr(DAIF_IRQ_BIT)
#define enable_fiq() write_daifclr(DAIF_FIQ_BIT)
#define enable_serror() write_daifclr(DAIF_ABT_BIT)
#define enable_debug_exceptions() write_daifclr(DAIF_DBG_BIT)
#define disable_irq() write_daifset(DAIF_IRQ_BIT)
#define disable_fiq() write_daifset(DAIF_FIQ_BIT)
#define disable_serror() write_daifset(DAIF_ABT_BIT)
#define disable_debug_exceptions() write_daifset(DAIF_DBG_BIT)
DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
DEFINE_SYSREG_READ_FUNC(CurrentEl)
DEFINE_SYSREG_RW_FUNCS(daif)
DEFINE_SYSREG_RW_FUNCS(spsr_el1)
DEFINE_SYSREG_RW_FUNCS(spsr_el2)
DEFINE_SYSREG_RW_FUNCS(spsr_el3)
DEFINE_SYSREG_RW_FUNCS(elr_el1)
DEFINE_SYSREG_RW_FUNCS(elr_el2)
DEFINE_SYSREG_RW_FUNCS(elr_el3)
DEFINE_SYSOP_FUNC(wfi)
DEFINE_SYSOP_FUNC(wfe)
DEFINE_SYSOP_FUNC(sev)
DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
DEFINE_SYSOP_FUNC(isb)
uint32_t get_afflvl_shift(uint32_t);
uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
/*******************************************************************************
* System register accessor prototypes
******************************************************************************/
unsigned long read_midr(void);
unsigned long read_mpidr(void);
DEFINE_SYSREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)
unsigned long read_scr(void);
unsigned long read_hcr(void);
unsigned long read_vbar_el1(void);
unsigned long read_vbar_el2(void);
unsigned long read_vbar_el3(void);
unsigned long read_sctlr_el1(void);
unsigned long read_sctlr_el2(void);
unsigned long read_sctlr_el3(void);
unsigned long read_actlr_el1(void);
unsigned long read_actlr_el2(void);
unsigned long read_actlr_el3(void);
unsigned long read_esr_el1(void);
unsigned long read_esr_el2(void);
unsigned long read_esr_el3(void);
unsigned long read_afsr0_el1(void);
unsigned long read_afsr0_el2(void);
unsigned long read_afsr0_el3(void);
unsigned long read_afsr1_el1(void);
unsigned long read_afsr1_el2(void);
unsigned long read_afsr1_el3(void);
unsigned long read_far_el1(void);
unsigned long read_far_el2(void);
unsigned long read_far_el3(void);
DEFINE_SYSREG_RW_FUNCS(scr_el3)
DEFINE_SYSREG_RW_FUNCS(hcr_el2)
unsigned long read_mair_el1(void);
unsigned long read_mair_el2(void);
unsigned long read_mair_el3(void);
DEFINE_SYSREG_RW_FUNCS(vbar_el1)
DEFINE_SYSREG_RW_FUNCS(vbar_el2)
DEFINE_SYSREG_RW_FUNCS(vbar_el3)
unsigned long read_amair_el1(void);
unsigned long read_amair_el2(void);
unsigned long read_amair_el3(void);
DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
unsigned long read_rvbar_el1(void);
unsigned long read_rvbar_el2(void);
unsigned long read_rvbar_el3(void);
DEFINE_SYSREG_RW_FUNCS(actlr_el1)
DEFINE_SYSREG_RW_FUNCS(actlr_el2)
DEFINE_SYSREG_RW_FUNCS(actlr_el3)
unsigned long read_rmr_el1(void);
unsigned long read_rmr_el2(void);
unsigned long read_rmr_el3(void);
DEFINE_SYSREG_RW_FUNCS(esr_el1)
DEFINE_SYSREG_RW_FUNCS(esr_el2)
DEFINE_SYSREG_RW_FUNCS(esr_el3)
unsigned long read_tcr_el1(void);
unsigned long read_tcr_el2(void);
unsigned long read_tcr_el3(void);
DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
unsigned long read_ttbr0_el1(void);
unsigned long read_ttbr0_el2(void);
unsigned long read_ttbr0_el3(void);
DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
unsigned long read_ttbr1_el1(void);
DEFINE_SYSREG_RW_FUNCS(far_el1)
DEFINE_SYSREG_RW_FUNCS(far_el2)
DEFINE_SYSREG_RW_FUNCS(far_el3)
unsigned long read_cptr_el2(void);
unsigned long read_cptr_el3(void);
DEFINE_SYSREG_RW_FUNCS(mair_el1)
DEFINE_SYSREG_RW_FUNCS(mair_el2)
DEFINE_SYSREG_RW_FUNCS(mair_el3)
unsigned long read_cpacr(void);
unsigned long read_cpuectlr(void);
unsigned int read_cntfrq_el0(void);
unsigned int read_cntps_ctl_el1(void);
unsigned int read_cntps_tval_el1(void);
unsigned long read_cntps_cval_el1(void);
unsigned long read_cntpct_el0(void);
unsigned long read_cnthctl_el2(void);
DEFINE_SYSREG_RW_FUNCS(amair_el1)
DEFINE_SYSREG_RW_FUNCS(amair_el2)
DEFINE_SYSREG_RW_FUNCS(amair_el3)
unsigned long read_tpidr_el3(void);
DEFINE_SYSREG_READ_FUNC(rvbar_el1)
DEFINE_SYSREG_READ_FUNC(rvbar_el2)
DEFINE_SYSREG_READ_FUNC(rvbar_el3)
void write_scr(unsigned long);
void write_hcr(unsigned long);
void write_cpacr(unsigned long);
void write_cntfrq_el0(unsigned int);
void write_cntps_ctl_el1(unsigned int);
void write_cntps_tval_el1(unsigned int);
void write_cntps_cval_el1(unsigned long);
void write_cnthctl_el2(unsigned long);
DEFINE_SYSREG_RW_FUNCS(rmr_el1)
DEFINE_SYSREG_RW_FUNCS(rmr_el2)
DEFINE_SYSREG_RW_FUNCS(rmr_el3)
void write_vbar_el1(unsigned long);
void write_vbar_el2(unsigned long);
void write_vbar_el3(unsigned long);
DEFINE_SYSREG_RW_FUNCS(tcr_el1)
DEFINE_SYSREG_RW_FUNCS(tcr_el2)
DEFINE_SYSREG_RW_FUNCS(tcr_el3)
void write_sctlr_el1(unsigned long);
void write_sctlr_el2(unsigned long);
void write_sctlr_el3(unsigned long);
DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
void write_actlr_el1(unsigned long);
void write_actlr_el2(unsigned long);
void write_actlr_el3(unsigned long);
DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
void write_esr_el1(unsigned long);
void write_esr_el2(unsigned long);
void write_esr_el3(unsigned long);
DEFINE_SYSREG_RW_FUNCS(cptr_el2)
DEFINE_SYSREG_RW_FUNCS(cptr_el3)
void write_afsr0_el1(unsigned long);
void write_afsr0_el2(unsigned long);
void write_afsr0_el3(unsigned long);
DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
DEFINE_SYSREG_READ_FUNC(cntpct_el0)
DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
void write_afsr1_el1(unsigned long);
void write_afsr1_el2(unsigned long);
void write_afsr1_el3(unsigned long);
DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
void write_far_el1(unsigned long);
void write_far_el2(unsigned long);
void write_far_el3(unsigned long);
/* Implementation specific registers */
void write_mair_el1(unsigned long);
void write_mair_el2(unsigned long);
void write_mair_el3(unsigned long);
DEFINE_RENAME_SYSREG_RW_FUNCS(cpuectlr_el1, CPUECTLR_EL1)
void write_amair_el1(unsigned long);
void write_amair_el2(unsigned long);
void write_amair_el3(unsigned long);
/* GICv3 System Registers */
void write_rmr_el1(unsigned long);
void write_rmr_el2(unsigned long);
void write_rmr_el3(unsigned long);
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
void write_tcr_el1(unsigned long);
void write_tcr_el2(unsigned long);
void write_tcr_el3(unsigned long);
void write_ttbr0_el1(unsigned long);
void write_ttbr0_el2(unsigned long);
void write_ttbr0_el3(unsigned long);
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)
void write_ttbr1_el1(unsigned long);
#define IS_IN_EL1() IS_IN_EL(1)
#define IS_IN_EL3() IS_IN_EL(3)
void write_cpuectlr(unsigned long);
void write_cptr_el2(unsigned long);
void write_cptr_el3(unsigned long);
/* Previously defined accesor functions with incomplete register names */
void write_tpidr_el3(unsigned long);
#define read_current_el() read_CurrentEl()
#define IS_IN_EL(x) \
(GET_EL(read_current_el()) == MODE_EL##x)
#define dsb() dsbsy()
#define IS_IN_EL1() IS_IN_EL(1)
#define IS_IN_EL3() IS_IN_EL(3)
#define read_midr() read_midr_el1()
#define read_mpidr() read_mpidr_el1()
#define read_scr() read_scr_el3()
#define write_scr(_v) write_scr_el3(_v)
#define read_hcr() read_hcr_el2()
#define write_hcr(_v) write_hcr_el2(_v)
#define read_cpuectlr() read_cpuectlr_el1()
#define write_cpuectlr(_v) write_cpuectlr_el1(_v)
#define read_cpacr() read_cpacr_el1()
#define write_cpacr(_v) write_cpacr_el1(_v)
#endif /* __ARCH_HELPERS_H__ */

48
lib/aarch64/cache_helpers.S
View File

@ -31,59 +31,11 @@
#include <arch.h>
#include <asm_macros.S>
.globl dcisw
.globl dccisw
.globl dccsw
.globl dccvac
.globl dcivac
.globl dccivac
.globl dccvau
.globl dczva
.globl flush_dcache_range
.globl inv_dcache_range
.globl dcsw_op_louis
.globl dcsw_op_all
func dcisw
dc isw, x0
ret
func dccisw
dc cisw, x0
ret
func dccsw
dc csw, x0
ret
func dccvac
dc cvac, x0
ret
func dcivac
dc ivac, x0
ret
func dccivac
dc civac, x0
ret
func dccvau
dc cvau, x0
ret
func dczva
dc zva, x0
ret
/* ------------------------------------------
* Clean+Invalidate from base address till
* size. 'x0' = addr, 'x1' = size

195
lib/aarch64/misc_helpers.S
View File

@ -31,44 +31,8 @@
#include <arch.h>
#include <asm_macros.S>
.globl enable_irq
.globl disable_irq
.globl enable_fiq
.globl disable_fiq
.globl enable_serror
.globl disable_serror
.globl enable_debug_exceptions
.globl disable_debug_exceptions
.globl read_daif
.globl write_daif
.globl read_spsr_el1
.globl read_spsr_el2
.globl read_spsr_el3
.globl write_spsr_el1
.globl write_spsr_el2
.globl write_spsr_el3
.globl read_elr_el1
.globl read_elr_el2
.globl read_elr_el3
.globl write_elr_el1
.globl write_elr_el2
.globl write_elr_el3
.globl get_afflvl_shift
.globl mpidr_mask_lower_afflvls
.globl dsb
.globl isb
.globl sev
.globl wfe
.globl wfi
.globl eret
.globl smc
@ -78,6 +42,10 @@
.globl disable_mmu_el3
.globl disable_mmu_icache_el3
#if SUPPORT_VFP
.globl enable_vfp
#endif
func get_afflvl_shift
cmp x0, #3
@ -95,144 +63,6 @@ func mpidr_mask_lower_afflvls
lsl x0, x0, x2
ret
/* -----------------------------------------------------
* Asynchronous exception manipulation accessors
* -----------------------------------------------------
*/
func enable_irq
msr daifclr, #DAIF_IRQ_BIT
ret
func enable_fiq
msr daifclr, #DAIF_FIQ_BIT
ret
func enable_serror
msr daifclr, #DAIF_ABT_BIT
ret
func enable_debug_exceptions
msr daifclr, #DAIF_DBG_BIT
ret
func disable_irq
msr daifset, #DAIF_IRQ_BIT
ret
func disable_fiq
msr daifset, #DAIF_FIQ_BIT
ret
func disable_serror
msr daifset, #DAIF_ABT_BIT
ret
func disable_debug_exceptions
msr daifset, #DAIF_DBG_BIT
ret
func read_daif
mrs x0, daif
ret
func write_daif
msr daif, x0
ret
func read_spsr_el1
mrs x0, spsr_el1
ret
func read_spsr_el2
mrs x0, spsr_el2
ret
func read_spsr_el3
mrs x0, spsr_el3
ret
func write_spsr_el1
msr spsr_el1, x0
ret
func write_spsr_el2
msr spsr_el2, x0
ret
func write_spsr_el3
msr spsr_el3, x0
ret
func read_elr_el1
mrs x0, elr_el1
ret
func read_elr_el2
mrs x0, elr_el2
ret
func read_elr_el3
mrs x0, elr_el3
ret
func write_elr_el1
msr elr_el1, x0
ret
func write_elr_el2
msr elr_el2, x0
ret
func write_elr_el3
msr elr_el3, x0
ret
func dsb
dsb sy
ret
func isb
isb
ret
func sev
sev
ret
func wfe
wfe
ret
func wfi
wfi
ret
func eret
eret
@ -315,3 +145,20 @@ func disable_mmu_icache_el3
mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
b do_disable_mmu
/* ---------------------------------------------------------------------------
* Enable the use of VFP at EL3
* ---------------------------------------------------------------------------
*/
#if SUPPORT_VFP
func enable_vfp
mrs x0, cpacr_el1
orr x0, x0, #CPACR_VFP_BITS
msr cpacr_el1, x0
mrs x0, cptr_el3
mov x1, #AARCH64_CPTR_TFP
bic x0, x0, x1
msr cptr_el3, x0
isb
ret
#endif

782
lib/aarch64/sysreg_helpers.S
View File

@ -1,782 +0,0 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <asm_macros.S>
.globl read_vbar_el1
.globl read_vbar_el2
.globl read_vbar_el3
.globl write_vbar_el1
.globl write_vbar_el2
.globl write_vbar_el3
.globl read_sctlr_el1
.globl read_sctlr_el2
.globl read_sctlr_el3
.globl write_sctlr_el1
.globl write_sctlr_el2
.globl write_sctlr_el3
.globl read_actlr_el1
.globl read_actlr_el2
.globl read_actlr_el3
.globl write_actlr_el1
.globl write_actlr_el2
.globl write_actlr_el3
.globl read_esr_el1
.globl read_esr_el2
.globl read_esr_el3
.globl write_esr_el1
.globl write_esr_el2
.globl write_esr_el3
.globl read_afsr0_el1
.globl read_afsr0_el2
.globl read_afsr0_el3
.globl write_afsr0_el1
.globl write_afsr0_el2
.globl write_afsr0_el3
.globl read_afsr1_el1
.globl read_afsr1_el2
.globl read_afsr1_el3
.globl write_afsr1_el1
.globl write_afsr1_el2
.globl write_afsr1_el3
.globl read_far_el1
.globl read_far_el2
.globl read_far_el3
.globl write_far_el1
.globl write_far_el2
.globl write_far_el3
.globl read_mair_el1
.globl read_mair_el2
.globl read_mair_el3
.globl write_mair_el1
.globl write_mair_el2
.globl write_mair_el3
.globl read_amair_el1
.globl read_amair_el2
.globl read_amair_el3
.globl write_amair_el1
.globl write_amair_el2
.globl write_amair_el3
.globl read_rvbar_el1
.globl read_rvbar_el2
.globl read_rvbar_el3
.globl read_rmr_el1
.globl read_rmr_el2
.globl read_rmr_el3
.globl write_rmr_el1
.globl write_rmr_el2
.globl write_rmr_el3
.globl read_tcr_el1
.globl read_tcr_el2
.globl read_tcr_el3
.globl write_tcr_el1
.globl write_tcr_el2
.globl write_tcr_el3
.globl read_cptr_el2
.globl read_cptr_el3
.globl write_cptr_el2
.globl write_cptr_el3
.globl read_ttbr0_el1
.globl read_ttbr0_el2
.globl read_ttbr0_el3
.globl write_ttbr0_el1
.globl write_ttbr0_el2
.globl write_ttbr0_el3
.globl read_ttbr1_el1
.globl write_ttbr1_el1
.globl read_cpacr
.globl write_cpacr
.globl read_cntfrq
.globl write_cntfrq
.globl read_cpuectlr
.globl write_cpuectlr
.globl read_cnthctl_el2
.globl write_cnthctl_el2
.globl read_cntfrq_el0
.globl write_cntfrq_el0
.globl read_cntps_ctl_el1
.globl write_cntps_ctl_el1
.globl read_cntps_cval_el1
.globl write_cntps_cval_el1
.globl read_cntps_tval_el1
.globl write_cntps_tval_el1
.globl read_scr
.globl write_scr
.globl read_hcr
.globl write_hcr
.globl read_midr
.globl read_mpidr
.globl read_cntpct_el0
.globl read_current_el
.globl read_id_pfr1_el1
.globl read_id_aa64pfr0_el1
.globl write_tpidr_el3
.globl read_tpidr_el3
#if SUPPORT_VFP
.globl enable_vfp
#endif
func read_current_el
mrs x0, CurrentEl
ret
func read_id_pfr1_el1
mrs x0, id_pfr1_el1
ret
func read_id_aa64pfr0_el1
mrs x0, id_aa64pfr0_el1
ret
/* -----------------------------------------------------
* VBAR accessors
* -----------------------------------------------------
*/
func read_vbar_el1
mrs x0, vbar_el1
ret
func read_vbar_el2
mrs x0, vbar_el2
ret
func read_vbar_el3
mrs x0, vbar_el3
ret
func write_vbar_el1
msr vbar_el1, x0
ret
func write_vbar_el2
msr vbar_el2, x0
ret
func write_vbar_el3
msr vbar_el3, x0
ret
/* -----------------------------------------------------
* AFSR0 accessors
* -----------------------------------------------------
*/
func read_afsr0_el1
mrs x0, afsr0_el1
ret
func read_afsr0_el2
mrs x0, afsr0_el2
ret
func read_afsr0_el3
mrs x0, afsr0_el3
ret
func write_afsr0_el1
msr afsr0_el1, x0
ret
func write_afsr0_el2
msr afsr0_el2, x0
ret
func write_afsr0_el3
msr afsr0_el3, x0
ret
/* -----------------------------------------------------
* FAR accessors
* -----------------------------------------------------
*/
func read_far_el1
mrs x0, far_el1
ret
func read_far_el2
mrs x0, far_el2
ret
func read_far_el3
mrs x0, far_el3
ret
func write_far_el1
msr far_el1, x0
ret
func write_far_el2
msr far_el2, x0
ret
func write_far_el3
msr far_el3, x0
ret
/* -----------------------------------------------------
* MAIR accessors
* -----------------------------------------------------
*/
func read_mair_el1
mrs x0, mair_el1
ret
func read_mair_el2
mrs x0, mair_el2
ret
func read_mair_el3
mrs x0, mair_el3
ret
func write_mair_el1
msr mair_el1, x0
ret
func write_mair_el2
msr mair_el2, x0
ret
func write_mair_el3
msr mair_el3, x0
ret
/* -----------------------------------------------------
* AMAIR accessors
* -----------------------------------------------------
*/
func read_amair_el1
mrs x0, amair_el1
ret
func read_amair_el2
mrs x0, amair_el2
ret
func read_amair_el3
mrs x0, amair_el3
ret
func write_amair_el1
msr amair_el1, x0
ret
func write_amair_el2
msr amair_el2, x0
ret
func write_amair_el3
msr amair_el3, x0
ret
/* -----------------------------------------------------
* RVBAR accessors
* -----------------------------------------------------
*/
func read_rvbar_el1
mrs x0, rvbar_el1
ret
func read_rvbar_el2
mrs x0, rvbar_el2
ret
func read_rvbar_el3
mrs x0, rvbar_el3
ret
/* -----------------------------------------------------
* RMR accessors
* -----------------------------------------------------
*/
func read_rmr_el1
mrs x0, rmr_el1
ret
func read_rmr_el2
mrs x0, rmr_el2
ret
func read_rmr_el3
mrs x0, rmr_el3
ret
func write_rmr_el1
msr rmr_el1, x0
ret
func write_rmr_el2
msr rmr_el2, x0
ret
func write_rmr_el3
msr rmr_el3, x0
ret
/* -----------------------------------------------------
* AFSR1 accessors
* -----------------------------------------------------
*/
func read_afsr1_el1
mrs x0, afsr1_el1
ret
func read_afsr1_el2
mrs x0, afsr1_el2
ret
func read_afsr1_el3
mrs x0, afsr1_el3
ret
func write_afsr1_el1
msr afsr1_el1, x0
ret
func write_afsr1_el2
msr afsr1_el2, x0
ret
func write_afsr1_el3
msr afsr1_el3, x0
ret
/* -----------------------------------------------------
* SCTLR accessors
* -----------------------------------------------------
*/
func read_sctlr_el1
mrs x0, sctlr_el1
ret
func read_sctlr_el2
mrs x0, sctlr_el2
ret
func read_sctlr_el3
mrs x0, sctlr_el3
ret
func write_sctlr_el1
msr sctlr_el1, x0
ret
func write_sctlr_el2
msr sctlr_el2, x0
ret
func write_sctlr_el3
msr sctlr_el3, x0
ret
/* -----------------------------------------------------
* ACTLR accessors
* -----------------------------------------------------
*/
func read_actlr_el1
mrs x0, actlr_el1
ret
func read_actlr_el2
mrs x0, actlr_el2
ret
func read_actlr_el3
mrs x0, actlr_el3
ret
func write_actlr_el1
msr actlr_el1, x0
ret
func write_actlr_el2
msr actlr_el2, x0
ret
func write_actlr_el3
msr actlr_el3, x0
ret
/* -----------------------------------------------------
* ESR accessors
* -----------------------------------------------------
*/
func read_esr_el1
mrs x0, esr_el1
ret
func read_esr_el2
mrs x0, esr_el2
ret
func read_esr_el3
mrs x0, esr_el3
ret
func write_esr_el1
msr esr_el1, x0
ret
func write_esr_el2
msr esr_el2, x0
ret
func write_esr_el3
msr esr_el3, x0
ret
/* -----------------------------------------------------
* TCR accessors
* -----------------------------------------------------
*/
func read_tcr_el1
mrs x0, tcr_el1
ret
func read_tcr_el2
mrs x0, tcr_el2
ret
func read_tcr_el3
mrs x0, tcr_el3
ret
func write_tcr_el1
msr tcr_el1, x0
ret
func write_tcr_el2
msr tcr_el2, x0
ret
func write_tcr_el3
msr tcr_el3, x0
ret
/* -----------------------------------------------------
* CPTR accessors
* -----------------------------------------------------
*/
func read_cptr_el2
mrs x0, cptr_el2
ret
func read_cptr_el3
mrs x0, cptr_el3
ret
func write_cptr_el2
msr cptr_el2, x0
ret
func write_cptr_el3
msr cptr_el3, x0
ret
/* -----------------------------------------------------
* TTBR0 accessors
* -----------------------------------------------------
*/
func read_ttbr0_el1
mrs x0, ttbr0_el1
ret
func read_ttbr0_el2
mrs x0, ttbr0_el2
ret
func read_ttbr0_el3
mrs x0, ttbr0_el3
ret
func write_ttbr0_el1
msr ttbr0_el1, x0
ret
func write_ttbr0_el2
msr ttbr0_el2, x0
ret
func write_ttbr0_el3
msr ttbr0_el3, x0
ret
/* -----------------------------------------------------
* TTBR1 accessors
* -----------------------------------------------------
*/
func read_ttbr1_el1
mrs x0, ttbr1_el1
ret
func write_ttbr1_el1
msr ttbr1_el1, x0
ret
func read_hcr
mrs x0, hcr_el2
ret
func write_hcr
msr hcr_el2, x0
ret
func read_cpacr
mrs x0, cpacr_el1
ret
func write_cpacr
msr cpacr_el1, x0
ret
func read_cntfrq_el0
mrs x0, cntfrq_el0
ret
func write_cntfrq_el0
msr cntfrq_el0, x0
ret
func read_cntps_ctl_el1
mrs x0, cntps_ctl_el1
ret
func write_cntps_ctl_el1
msr cntps_ctl_el1, x0
ret
func read_cntps_cval_el1
mrs x0, cntps_cval_el1
ret
func write_cntps_cval_el1
msr cntps_cval_el1, x0
ret
func read_cntps_tval_el1
mrs x0, cntps_tval_el1
ret
func write_cntps_tval_el1
msr cntps_tval_el1, x0
ret
func read_cntpct_el0
mrs x0, cntpct_el0
ret
func read_cpuectlr
mrs x0, CPUECTLR_EL1
ret
func write_cpuectlr
msr CPUECTLR_EL1, x0
ret
func read_cnthctl_el2
mrs x0, cnthctl_el2
ret
func write_cnthctl_el2
msr cnthctl_el2, x0
ret
func read_cntfrq
mrs x0, cntfrq_el0
ret
func write_cntfrq
msr cntfrq_el0, x0
ret
func write_scr
msr scr_el3, x0
ret
func read_scr
mrs x0, scr_el3
ret
func read_midr
mrs x0, midr_el1
ret
func read_mpidr
mrs x0, mpidr_el1
ret
func write_tpidr_el3
msr tpidr_el3, x0
ret
func read_tpidr_el3
mrs x0, tpidr_el3
ret
#if SUPPORT_VFP
func enable_vfp
mrs x0, cpacr_el1
orr x0, x0, #CPACR_VFP_BITS
msr cpacr_el1, x0
mrs x0, cptr_el3
mov x1, #AARCH64_CPTR_TFP
bic x0, x0, x1
msr cptr_el3, x0
isb
ret
#endif

73
lib/aarch64/tlb_helpers.S
View File

@ -1,73 +0,0 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <asm_macros.S>
.globl tlbialle1
.globl tlbialle1is
.globl tlbialle2
.globl tlbialle2is
.globl tlbialle3
.globl tlbialle3is
.globl tlbivmalle1
func tlbialle1
tlbi alle1
ret
func tlbialle1is
tlbi alle1is
ret
func tlbialle2
tlbi alle2
ret
func tlbialle2is
tlbi alle2is
ret
func tlbialle3
tlbi alle3
ret
func tlbialle3is
tlbi alle3is
ret
func tlbivmalle1
tlbi vmalle1
ret

2
plat/fvp/platform.mk
View File

@ -51,7 +51,6 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \
drivers/io/io_memmap.c \
drivers/io/io_semihosting.c \
lib/mmio.c \
lib/aarch64/sysreg_helpers.S \
lib/aarch64/xlat_tables.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
@ -72,7 +71,6 @@ BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
BL31_SOURCES += drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/arm/gic/aarch64/gic_v3_sysregs.S \
drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_mp_stack.S \
plat/fvp/bl31_fvp_setup.c \

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