From aa09622233a891cb04c65a5db816e0dc76110e21 Mon Sep 17 00:00:00 2001 From: Kevin Chen Date: Tue, 9 Jul 2024 18:15:28 +0800 Subject: [PATCH] fix(ast2700): fix mpll calculate statement pll_reg.b.bypass equal to 1U, bypass the mpll calculating pll_reg.b.bypass equal to 0U, need to calculate mpll Change-Id: I6cace1509d9429a97c7c9481dc1e2e4f95134d6c Signed-off-by: Kevin Chen --- plat/aspeed/ast2700/plat_bl31_setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c index 9fec3e8ec..087b47953 100644 --- a/plat/aspeed/ast2700/plat_bl31_setup.c +++ b/plat/aspeed/ast2700/plat_bl31_setup.c @@ -174,7 +174,7 @@ static uint32_t plat_get_pll_rate(int pll_idx) break; } } else { - if (pll_reg.b.bypass != 0U) { + if (pll_reg.b.bypass == 0U) { if (pll_idx == PLAT_CLK_MPLL) { /* F = 25Mhz * [M / (n + 1)] / (p + 1) */ mul = (pll_reg.b.m) / ((pll_reg.b.n + 1));