From 5e0be8c0241e5075b34bd5b14df2df9f048715d3 Mon Sep 17 00:00:00 2001
From: Yann Gautier <yann.gautier@st.com>
Date: Tue, 21 May 2024 20:54:04 +0200
Subject: [PATCH] feat(stm32mp2): enable DDR sub-system clock

Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver init,
as it needs to be done before enabling DDR PLL clock (PLL2).

Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193
Signed-off-by: Yann Gautier <yann.gautier@st.com>
---
 drivers/st/ddr/stm32mp2_ddr_helpers.c     | 15 +++++++++++++++
 include/drivers/st/stm32mp2_ddr_helpers.h | 12 ++++++++++++
 plat/st/stm32mp2/bl2_plat_setup.c         |  7 +++++++
 plat/st/stm32mp2/platform.mk              |  2 ++
 4 files changed, 36 insertions(+)
 create mode 100644 drivers/st/ddr/stm32mp2_ddr_helpers.c
 create mode 100644 include/drivers/st/stm32mp2_ddr_helpers.h

diff --git a/drivers/st/ddr/stm32mp2_ddr_helpers.c b/drivers/st/ddr/stm32mp2_ddr_helpers.c
new file mode 100644
index 000000000..e6be9ddaa
--- /dev/null
+++ b/drivers/st/ddr/stm32mp2_ddr_helpers.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+void ddr_sub_system_clk_init(void)
+{
+	mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
+		      RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN);
+}
diff --git a/include/drivers/st/stm32mp2_ddr_helpers.h b/include/drivers/st/stm32mp2_ddr_helpers.h
new file mode 100644
index 000000000..069fb83db
--- /dev/null
+++ b/include/drivers/st/stm32mp2_ddr_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP2_DDR_HELPERS_H
+#define STM32MP2_DDR_HELPERS_H
+
+void ddr_sub_system_clk_init(void);
+
+#endif /* STM32MP2_DDR_HELPERS_H */
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 77b143fbf..40c182cf4 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -10,6 +10,7 @@
 #include <common/debug.h>
 #include <drivers/clk.h>
 #include <drivers/st/regulator_fixed.h>
+#include <drivers/st/stm32mp2_ddr_helpers.h>
 #include <lib/fconf/fconf.h>
 #include <lib/fconf/fconf_dyn_cfg_getter.h>
 #include <lib/mmio.h>
@@ -186,6 +187,12 @@ void bl2_el3_plat_arch_setup(void)
 
 	reset_backup_domain();
 
+	/*
+	 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2),
+	 * and so before stm32mp2_clk_init().
+	 */
+	ddr_sub_system_clk_init();
+
 	if (stm32mp2_clk_init() < 0) {
 		panic();
 	}
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 2b789c690..c9cda3ec6 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -90,5 +90,7 @@ ifeq (${STM32MP_USB_PROGRAMMER},1)
 BL2_SOURCES			+=	plat/st/stm32mp2/stm32mp2_usb_dfu.c
 endif
 
+BL2_SOURCES			+=	drivers/st/ddr/stm32mp2_ddr_helpers.c
+
 # Compilation rules
 include plat/st/common/common_rules.mk