From 5e21d795b45dc21e33dcd9c8453d6f4ca923ce3a Mon Sep 17 00:00:00 2001 From: Soby Mathew Date: Wed, 14 Sep 2016 15:51:44 +0100 Subject: [PATCH] AArch32: Update user-guide and add DTBs This patch adds necessary updates for building and running Trusted Firmware for AArch32 to user-guide.md. The instructions for running on both `FVP_Base_AEMv8A-AEMv8A` in AArch32 mode and `FVP_Base_Cortex-A32x4` models are added. The device tree files for AArch32 Linux kernel are also added in the `fdts` folder. Change-Id: I0023b6b03e05f32637cb5765fdeda8c8df2d0d3e --- docs/user-guide.md | 178 ++++++++++++-- fdts/fvp-base-gicv2-psci-aarch32.dtb | Bin 0 -> 10336 bytes fdts/fvp-base-gicv2-psci-aarch32.dts | 331 ++++++++++++++++++++++++++ fdts/fvp-base-gicv3-psci-aarch32.dtb | Bin 0 -> 10803 bytes fdts/fvp-base-gicv3-psci-aarch32.dts | 340 +++++++++++++++++++++++++++ 5 files changed, 834 insertions(+), 15 deletions(-) create mode 100644 fdts/fvp-base-gicv2-psci-aarch32.dtb create mode 100644 fdts/fvp-base-gicv2-psci-aarch32.dts create mode 100644 fdts/fvp-base-gicv3-psci-aarch32.dtb create mode 100644 fdts/fvp-base-gicv3-psci-aarch32.dts diff --git a/docs/user-guide.md b/docs/user-guide.md index a07185d49..051f92009 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -89,23 +89,50 @@ Download the Trusted Firmware source code from Github: --------------------------------- * Before building Trusted Firmware, the environment variable `CROSS_COMPILE` - must point to the Linaro cross compiler: + must point to the Linaro cross compiler. + + For AArch64: export CROSS_COMPILE=/bin/aarch64-linux-gnu- -* Change to the root directory of the Trusted Firmware source tree and build: + For AArch32: + + export CROSS_COMPILE=/bin/arm-linux-gnueabihf- + +* Change to the root directory of the Trusted Firmware source tree and build. + + For AArch64: make PLAT= all - Notes: + For AArch32: + + make PLAT= ARCH=aarch32 AARCH32_SP=sp_min all + + + Notes: * If `PLAT` is not specified, `fvp` is assumed by default. See the "Summary of build options" for more information on available build options. - * The TSP (Test Secure Payload), corresponding to the BL32 image, is not - compiled in by default. Refer to the "Building the Test Secure Payload" - section below. + * (AArch32 only) Currently only `PLAT=fvp` is supported. Please note that + AArch32 support for Normal world boot loader (BL33), like U-boot or + UEFI, on FVP is not available upstream. Hence custom solutions are + required to allow Linux boot on FVP. The build instructions below + assume such a custom boot loader (BL33) is available. + + * (AArch32 only) `AARCH32_SP` is the AArch32 EL3 Runtime Software and it + corresponds to the BL32 image. A minimal `AARCH32_SP`, sp_min, is + provided by ARM Trusted Firmware to demonstrate how PSCI Library can + be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3 + Runtime Software may include other runtime services, for example + Trusted OS services. A guide to integrate PSCI library with AArch32 + EL3 Runtime Software can be found [here][PSCI Lib Integration]. + + * (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32 + image, is not compiled in by default. Refer to the "Building the Test + Secure Payload" section below. * By default this produces a release version of the build. To produce a debug version instead, refer to the "Debugging options" section below. @@ -117,7 +144,8 @@ Download the Trusted Firmware source code from Github: * `build///bl1.bin` * `build///bl2.bin` - * `build///bl31.bin` + * `build///bl31.bin` (AArch64 only) + * `build///bl32.bin` (mandatory for AArch32) where `` is the name of the chosen platform and `` is either `debug` or `release`. The actual number of images might differ @@ -238,6 +266,12 @@ performed. entrypoint) or 1 (CPU reset to BL31 entrypoint). The default value is 0. +* `RESET_TO_SP_MIN`: SP_MIN is the minimal AArch32 Secure Payload provided in + ARM Trusted Firmware. This flag configures SP_MIN entrypoint as the CPU + reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU + reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default + value is 0. + * `CRASH_REPORTING`: A non-zero value enables a console dump of processor register state when an unexpected exception occurs during execution of BL31. This option defaults to the value of `DEBUG` - i.e. by default @@ -600,7 +634,6 @@ An additional boot loader binary file is created in the `build` directory: `build///bl32.bin` - ### Checking source code style When making changes to the source for submission to the project, the source @@ -1042,8 +1075,8 @@ JTAG on Juno. 9. Running the software on FVP ------------------------------- -This version of the ARM Trusted Firmware has been tested on the following ARM -FVPs (64-bit versions only). +The AArch64 build of this version of ARM Trusted Firmware has been tested on +the following ARM FVPs (64-bit host machine only). * `Foundation_Platform` (Version 10.1, Build 10.1.32) * `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) @@ -1051,6 +1084,12 @@ FVPs (64-bit versions only). * `FVP_Base_Cortex-A57x1-A53x1` (Version 7.7, Build 0.8.7701) * `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701) +The AArch32 build of this version of ARM Trusted Firmware has been tested on +the following ARM FVPs (64-bit host machine only). + +* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32) + NOTE: The build numbers quoted above are those reported by launching the FVP with the `--version` parameter. @@ -1082,11 +1121,21 @@ all FDTs are available from there. For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base memory map configuration. +* `fvp-base-gicv2-psci-aarch32.dtb` + + For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state + with Base memory map configuration. + * `fvp-base-gicv3-psci.dtb` (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base memory map configuration and Linux GICv3 support. +* `fvp-base-gicv3-psci-aarch32.dtb` + + For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state + with Base memory map configuration and Linux GICv3 support. + * `fvp-foundation-gicv2-psci.dtb` For use with Foundation FVP with Base memory map configuration. @@ -1099,7 +1148,7 @@ all FDTs are available from there. ### Running on the Foundation FVP with reset to BL1 entrypoint The following `Foundation_Platform` parameters should be used to boot Linux with -4 CPUs using the ARM Trusted Firmware. +4 CPUs using the AArch64 build of ARM Trusted Firmware. /Foundation_Platform \ --cores=4 \ @@ -1124,7 +1173,7 @@ Notes: ### Running on the AEMv8 Base FVP with reset to BL1 entrypoint The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux -with 8 CPUs using the ARM Trusted Firmware. +with 8 CPUs using the AArch64 build of ARM Trusted Firmware. /FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ @@ -1139,10 +1188,36 @@ with 8 CPUs using the ARM Trusted Firmware. --data cluster0.cpu0="/"@0x80080000 \ -C bp.virtioblockdevice.image_path="/" +### Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint + +The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux +with 8 CPUs using the AArch32 build of ARM Trusted Firmware. + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.CONFIG64=0 \ + -C cluster0.cpu1.CONFIG64=0 \ + -C cluster0.cpu2.CONFIG64=0 \ + -C cluster0.cpu3.CONFIG64=0 \ + -C cluster1.cpu0.CONFIG64=0 \ + -C cluster1.cpu1.CONFIG64=0 \ + -C cluster1.cpu2.CONFIG64=0 \ + -C cluster1.cpu3.CONFIG64=0 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + ### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to -boot Linux with 8 CPUs using the ARM Trusted Firmware. +boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware. /FVP_Base_Cortex-A57x4-A53x4 \ -C pctl.startup=0.0.0.0 \ @@ -1155,10 +1230,26 @@ boot Linux with 8 CPUs using the ARM Trusted Firmware. --data cluster0.cpu0="/"@0x80080000 \ -C bp.virtioblockdevice.image_path="/" +### Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint + +The following `FVP_Base_Cortex-A32x4` model parameters should be used to +boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware. + + /FVP_Base_Cortex-A32x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + ### Running on the AEMv8 Base FVP with reset to BL31 entrypoint The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux -with 8 CPUs using the ARM Trusted Firmware. +with 8 CPUs using the AArch64 build of ARM Trusted Firmware. /FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ @@ -1199,10 +1290,47 @@ Notes: `--data=""@` to the new value of `BL32_BASE`. +### Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint + +The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux +with 8 CPUs using the AArch32 build of ARM Trusted Firmware. + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.CONFIG64=0 \ + -C cluster0.cpu1.CONFIG64=0 \ + -C cluster0.cpu2.CONFIG64=0 \ + -C cluster0.cpu3.CONFIG64=0 \ + -C cluster1.cpu0.CONFIG64=0 \ + -C cluster1.cpu1.CONFIG64=0 \ + -C cluster1.cpu2.CONFIG64=0 \ + -C cluster1.cpu3.CONFIG64=0 \ + -C cluster0.cpu0.RVBAR=0x04001000 \ + -C cluster0.cpu1.RVBAR=0x04001000 \ + -C cluster0.cpu2.RVBAR=0x04001000 \ + -C cluster0.cpu3.RVBAR=0x04001000 \ + -C cluster1.cpu0.RVBAR=0x04001000 \ + -C cluster1.cpu1.RVBAR=0x04001000 \ + -C cluster1.cpu2.RVBAR=0x04001000 \ + -C cluster1.cpu3.RVBAR=0x04001000 \ + --data cluster0.cpu0="/"@0x04001000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +Note: The load address of `` depends on the value `BL32_BASE`. +It should match the address programmed into the RVBAR register as well. + ### Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to -boot Linux with 8 CPUs using the ARM Trusted Firmware. +boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware. /FVP_Base_Cortex-A57x4-A53x4 \ -C pctl.startup=0.0.0.0 \ @@ -1224,6 +1352,25 @@ boot Linux with 8 CPUs using the ARM Trusted Firmware. --data cluster0.cpu0="/"@0x80080000 \ -C bp.virtioblockdevice.image_path="/" +### Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint + +The following `FVP_Base_Cortex-A32x4` model parameters should be used to +boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware. + + /FVP_Base_Cortex-A32x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBARADDR=0x04001000 \ + -C cluster0.cpu1.RVBARADDR=0x04001000 \ + -C cluster0.cpu2.RVBARADDR=0x04001000 \ + -C cluster0.cpu3.RVBARADDR=0x04001000 \ + --data cluster0.cpu0="/"@0x04001000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" 10. Running the software on Juno --------------------------------- @@ -1280,3 +1427,4 @@ _Copyright (c) 2013-2016, ARM Limited and Contributors. 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All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, + <0x0 0x2c000000 0 0x2000>, + <0x0 0x2c010000 0 0x2000>, + <0x0 0x2c02F000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/fdts/fvp-base-gicv3-psci-aarch32.dtb b/fdts/fvp-base-gicv3-psci-aarch32.dtb new file mode 100644 index 0000000000000000000000000000000000000000..474b18885c3e4bafe236889a5d39bfc0da469b59 GIT binary patch literal 10803 zcmb_i&5s;M6|bHpO9BZ_`2LRL4aTvy3Xkz z_3BrzUVU`;{P~eP|5WPano{a3N*(_N?k8|PhU-yWNJ~G3{yKBF`NQPt+uX0!E%-C&{arF*X1Td4chd#)Rnb?F~3E5eu^Kw|$_aEZ^U_ghal#pfb4pKg}|;ia#? zUZkNb_g|YGiwv?m7Q2wy7B7z7tB@ab zNimLcJvuBK<&hC=yKexmP7EZs{sWM!HZ-S-Z#}1F zQ%5-0aC)y>Uc-sL+>ev>ZOJR{Cy`%_gK;$vi1|6En-d@6-y(^k%ok6xpGR;>yi_)z z(LUh)*CtOt{obqv)<1uOj_Ze&-$K6c$ZsQ0ADeQIWBxuzrXMKlzG~n4hv6qJl z5L4dc&bZJ&7<13Zoi82b+4dQK)q02V zZ8aqVZTUg?y<71|PPTpK?Hu9y2YwQPw)`Oc-mUoK`fl4NH_FcVN(9>SgYaV=UWXlD z?j5#$^0WJmm$dyb2zT6lm}9>zN@S31J&vWjZqW{9_EY+rM(HTu>umBgg9NqI1!Tk zQ$6V|_sb|_-pJ}0^0aMb2Dp`x^}42v`GLt_wVZjVlqAy+2h>N6d{p08ji{7XtQuS? zH{Lb~DJKW`(fbzeL~?B0^^7`RhO0-vi!L4)bVJ)Z+hEH5U;Dua3?;fgZr=Az9<22k zoMO+J^qs%Fym6dHIrX|Ods*#;epyOhO~5VxN0j=X<@^CBkMSw>*b^mh`}Fz)|NR@= zsoL$dgH0@q&RPD$Zu`&b_I<<^>(NfxpOfFA3W+Q#zu7iSoA(q0-XIUsh+NiYxL|y| zUzrwY&yFA4<1>;Szlzg$S%joHl|IhW@~koEUzF$|rhV&QTKFO^+GpZf!sfr^7!|AeTPVxKsgKSy83*wv;W#R&78rD66%mFewwkzr5_%%A(k@RW& z8lAc6g~SNl8zs>pPF-X@&ST4oKL4#o$}jtjHkPUXgQI7* zcO4>_pT}@_?R*gOydCOX%!g_))VUZ=vw1tt)I+IKAF07m=i2#b4Td@w^RXHXbuNZe ze4dXp?NO@KCu%U%xpug2&fBqTDT*ZV%rK9k&b7nkWgg=!Ib!ECH5lq#JD;t=Q0HPE zufb5~Vvg2esB#LD4x!bVU(TRKT7;`fFnq2R zwp!xmS$kqo&s4Spo^pm{U9le~H{0v!&MVSl$we&>;@zn4hsh|s$s$|#9S28SuY1F1 zY&rG@?+%9Z3pF;0B@4D|ZE=q*dF0Um)moN`@yWgOP)E*mjBVJ|JZfxO9^9i`9+br& zy3Shrrgq7}d8pekCAP7DxjbfUS{~d_T^^K$$HJ?3TGd#t`}!Fn?FDkeoSi(zo}9hu zb1O4CtW0j4D@-g`>ZtsB#a@v|+nr|hSRm!)bAg?=z6P=q>*Fkg_@#CINkrRJjmJzm z`rCK{dG^ilk$B)9Z)L^s?QerH^e1JAKMr;-Q9qJulf+9s>N00s3DNw{0y*VOO0JeKk| zkhiggHp+h4zF~|T>x;vweS9-T_nxuc6PsmR!N(i>_K&Cks(;qU=#$u~Zf@)sKb*mfe5@TCKa6iX*Cl>#^+(%xiyv8^J1u8RTjaF9 zA1AIfi<}sn^fmTIS%0{OGx5&#%ksmSv$3u>muM(EgzOdgs_gDGCe{tt`S*=8{@a(U zu#lyd-0b?q{5)6kCz|^E;))sDY2AI@THAM>;1lkmPq~8`-sPH3`L26an1uaKs|+?` zOJ8LPkHq_|ReTy*9WSGrfEE4ZQ6z{oV&?TPt z9_99Ptk__%ESE*TAfYO`e{b!EdwyyBM76*6OQ-xdjtq6<&8ke!c$_`P5At4}vT#bn z5Lqc(!F}fWXceC!2Jv>y@z&aE{1tWNtS~ANhqR<^(f*7r9{?%U<@Eo*A#;xMA~)!k z9`?Q&WlMkj*IP!%x$_S4OvGRe^m!iUF#OUY^~BK*N5RTm&nfGEPIl#gG)*Xwh~ayp zS&pd&5r9ODOL7 z>lZGyyJxn}D#={9x+TS8<2cHHuyy(R#qPzev)9jGSCT*T!Zn?N^2XMcOIJ^{&`~C~ zdjhu~ZK0^Ub^2;|V`HPGD(RVxO4!`ov~|#jr5{6Jyu0J}5Q8C6;V8|5aokHHRei|I zf;<|I)k@Is^N(XbpOFf+QpB%BCSOE(93)Mp?|2C#a@*Y3REoC`qrSrT-)=D}vS_ID zqrpIQqoKlMS~nZrigM~GprvTcQiZnjJ$yS76Ij-Q#C%RF#-mKH%KWdDG3}wENQS8z$umm zX!+G2b_z9&c40i4Mv4AFt5z!SX>aAha2x*)a@6J5(MnmUw1}PWrb=F$_=7xpc|w{> zK5+TNN!r7=zRDKWCbzG!FC8bd-!;J=&<#2g$8qukaCA+_mkyhH@{+; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 0 0 4>, + <0 0 1 &gic 0 0 0 1 4>, + <0 0 2 &gic 0 0 0 2 4>, + <0 0 3 &gic 0 0 0 3 4>, + <0 0 4 &gic 0 0 0 4 4>, + <0 0 5 &gic 0 0 0 5 4>, + <0 0 6 &gic 0 0 0 6 4>, + <0 0 7 &gic 0 0 0 7 4>, + <0 0 8 &gic 0 0 0 8 4>, + <0 0 9 &gic 0 0 0 9 4>, + <0 0 10 &gic 0 0 0 10 4>, + <0 0 11 &gic 0 0 0 11 4>, + <0 0 12 &gic 0 0 0 12 4>, + <0 0 13 &gic 0 0 0 13 4>, + <0 0 14 &gic 0 0 0 14 4>, + <0 0 15 &gic 0 0 0 15 4>, + <0 0 16 &gic 0 0 0 16 4>, + <0 0 17 &gic 0 0 0 17 4>, + <0 0 18 &gic 0 0 0 18 4>, + <0 0 19 &gic 0 0 0 19 4>, + <0 0 20 &gic 0 0 0 20 4>, + <0 0 21 &gic 0 0 0 21 4>, + <0 0 22 &gic 0 0 0 22 4>, + <0 0 23 &gic 0 0 0 23 4>, + <0 0 24 &gic 0 0 0 24 4>, + <0 0 25 &gic 0 0 0 25 4>, + <0 0 26 &gic 0 0 0 26 4>, + <0 0 27 &gic 0 0 0 27 4>, + <0 0 28 &gic 0 0 0 28 4>, + <0 0 29 &gic 0 0 0 29 4>, + <0 0 30 &gic 0 0 0 30 4>, + <0 0 31 &gic 0 0 0 31 4>, + <0 0 32 &gic 0 0 0 32 4>, + <0 0 33 &gic 0 0 0 33 4>, + <0 0 34 &gic 0 0 0 34 4>, + <0 0 35 &gic 0 0 0 35 4>, + <0 0 36 &gic 0 0 0 36 4>, + <0 0 37 &gic 0 0 0 37 4>, + <0 0 38 &gic 0 0 0 38 4>, + <0 0 39 &gic 0 0 0 39 4>, + <0 0 40 &gic 0 0 0 40 4>, + <0 0 41 &gic 0 0 0 41 4>, + <0 0 42 &gic 0 0 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +};