Browse Source

Apply compile-time check for AArch64-only cores

Some cores support only AArch64 mode. In those cores, only a limited
subset of the AArch32 system registers are implemented. Hence, if TF-A
is supposed to run on AArch64-only cores, it must be compiled with
CTX_INCLUDE_AARCH32_REGS=0.

Currently, the default settings for compiling TF-A are with the AArch32
system registers included. So, if we compile TF-A the default way and
attempt to run it on an AArch64-only core, we only get a runtime panic.

Now a compile-time check has been added to ensure that this flag has the
appropriate value when AArch64-only cores are included in the build.

Change-Id: I298ec550037fafc9347baafb056926d149197d4c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
pull/1931/head
John Tsichritzis 6 years ago
parent
commit
629d04f530
  1. 5
      lib/cpus/aarch64/cortex_a76.S
  2. 5
      lib/cpus/aarch64/cortex_a76ae.S
  3. 5
      lib/cpus/aarch64/cortex_deimos.S
  4. 5
      lib/cpus/aarch64/neoverse_e1.S
  5. 5
      lib/cpus/aarch64/neoverse_n1.S
  6. 5
      lib/cpus/aarch64/neoverse_zeus.S
  7. 25
      plat/arm/board/fvp/platform.mk

5
lib/cpus/aarch64/cortex_a76.S

@ -18,6 +18,11 @@
#error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex-A76 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#define ESR_EL3_A64_SMC0 0x5e000000
#define ESR_EL3_A32_SMC0 0x4e000000

5
lib/cpus/aarch64/cortex_a76ae.S

@ -11,6 +11,11 @@
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
/* ---------------------------------------------

5
lib/cpus/aarch64/cortex_deimos.S

@ -14,6 +14,11 @@
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex-Deimos supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
/* ---------------------------------------------

5
lib/cpus/aarch64/neoverse_e1.S

@ -16,6 +16,11 @@
#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
func neoverse_e1_cpu_pwr_dwn
mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT

5
lib/cpus/aarch64/neoverse_n1.S

@ -15,6 +15,11 @@
#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata
* This applies to revision r0p0 and r1p0 of Neoverse N1.

5
lib/cpus/aarch64/neoverse_zeus.S

@ -14,6 +14,11 @@
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse-Zeus supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
/* ---------------------------------------------

25
plat/arm/board/fvp/platform.mk

@ -96,8 +96,8 @@ FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
ifeq (${ARCH}, aarch64)
# select a different set of CPU files, depending on whether we compile with
# hardware assisted coherency configurations or not
# select a different set of CPU files, depending on whether we compile for
# hardware assisted coherency cores or not
ifeq (${HW_ASSISTED_COHERENCY}, 0)
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
lib/cpus/aarch64/cortex_a53.S \
@ -105,14 +105,19 @@ ifeq (${HW_ASSISTED_COHERENCY}, 0)
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a73.S
else
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a75.S \
lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/cortex_deimos.S \
lib/cpus/aarch64/neoverse_zeus.S
# AArch64-only cores
ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/cortex_deimos.S \
lib/cpus/aarch64/neoverse_zeus.S
# AArch64/AArch32
else
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a75.S
endif
endif
else

Loading…
Cancel
Save