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@ -777,14 +777,6 @@ int socfpga_bridges_enable(uint32_t mask) |
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VERBOSE("Deassert F2SDRAM ...\n"); |
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VERBOSE("Deassert F2SDRAM ...\n"); |
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mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), |
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mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), |
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RSTMGR_BRGMODRST_F2SSDRAM0); |
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RSTMGR_BRGMODRST_F2SSDRAM0); |
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/*
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* Clear fpga2sdram_manager_main_SidebandManager_FlagOutClr0 |
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* f2s_ready_latency_enable |
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*/ |
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VERBOSE("Clear F2SDRAM f2s_ready_latency_enable ...\n"); |
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mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), |
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FLAGOUTCLR0_F2SDRAM0_ENABLE); |
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} |
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} |
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#else |
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#else |
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if (brg_mask != 0U) { |
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if (brg_mask != 0U) { |
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