feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0f46a4be96deac4d6a5a880c9f86ccf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

drivers/nxp/clk/s32cc/s32cc_clk_drv.c

@@ -340,6 +340,27 @@ static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long
 	return ret;
 }
 
+static int set_mux_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+			unsigned long *orate, unsigned int *depth)
+{
+	const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+	const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id);
+	int ret;
+
+	ret = update_stack_depth(depth);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (clk == NULL) {
+		ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n",
+		      mux->index, mux->source_id);
+		return -EINVAL;
+	}
+
+	return set_module_rate(&clk->desc, rate, orate, depth);
+}
+
 static int set_module_rate(const struct s32cc_clk_obj *module,
 			   unsigned long rate, unsigned long *orate,
 			   unsigned int *depth)
@@ -368,8 +389,10 @@ static int set_module_rate(const struct s32cc_clk_obj *module,
 		ret = set_fixed_div_freq(module, rate, orate, depth);
 		break;
 	case s32cc_clkmux_t:
+		ret = set_mux_freq(module, rate, orate, depth);
+		break;
 	case s32cc_shared_clkmux_t:
-		ret = -ENOTSUP;
+		ret = set_mux_freq(module, rate, orate, depth);
 		break;
 	default:
 		ret = -EINVAL;

drivers/nxp/clk/s32cc/s32cc_early_clks.c

@@ -11,6 +11,7 @@
 #define S32CC_FXOSC_FREQ	(40U * MHZ)
 #define S32CC_ARM_PLL_VCO_FREQ	(2U * GHZ)
 #define S32CC_ARM_PLL_PHI0_FREQ	(1U * GHZ)
+#define S32CC_A53_FREQ		(1U * GHZ)
 
 int s32cc_init_early_clks(void)
 {
@@ -43,6 +44,11 @@ int s32cc_init_early_clks(void)
 		return ret;
 	}
 
+	ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL);
+	if (ret != 0) {
+		return ret;
+	}
+
 	ret = clk_enable(S32CC_CLK_FXOSC);
 	if (ret != 0) {
 		return ret;