Browse Source
* changes: Tegra186: store TZDRAM base/size to scratch registers Tegra186: add SE support to generate SHA256 of TZRAM Tegra186: add support for bpmp_ipc driver Tegra210: disable ERRATA_A57_829520 Tegra194: memctrl: add support for MIU4 and MIU5 Tegra194: memctrl: remove support to reconfigure MSS Tegra: fiq_glue: remove bakery locks from interrupt handler Tegra210: SE: add context save support Tegra210: update the PMC blacklisted registers Tegra: disable CPUACTLR access from lower exception levels cpus: denver: fixup register used to store return addresspull/1938/head
Olivier Deprez
5 years ago
committed by
TrustedFirmware Code Review
TrustedFirmware Code Review
20 changed files with 614 additions and 552 deletions
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/*
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <assert.h> |
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#include <drivers/delay_timer.h> |
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#include <errno.h> |
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#include <string.h> |
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#include <bpmp_ipc.h> |
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#include <pmc.h> |
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#include <security_engine.h> |
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#include <tegra186_private.h> |
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#include <tegra_private.h> |
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#include "se_private.h" |
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/*******************************************************************************
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* Constants and Macros |
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******************************************************************************/ |
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#define SE0_MAX_BUSY_TIMEOUT_MS U(100) /* 100ms */ |
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#define BYTES_IN_WORD U(4) |
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#define SHA256_MAX_HASH_RESULT U(7) |
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#define SHA256_DST_SIZE U(32) |
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#define SHA_FIRST_OP U(1) |
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#define MAX_SHA_ENGINE_CHUNK_SIZE U(0xFFFFFF) |
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#define SHA256_MSG_LENGTH_ONETIME U(0xffff) |
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/*
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* Check that SE operation has completed after kickoff |
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* This function is invoked after an SE operation has been started, |
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* and it checks the following conditions: |
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* 1. SE0_INT_STATUS = SE0_OP_DONE |
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* 2. SE0_STATUS = IDLE |
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* 3. SE0_ERR_STATUS is clean. |
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*/ |
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static int32_t tegra_se_operation_complete(void) |
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{ |
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uint32_t val = 0U; |
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/* Read SE0 interrupt register to ensure H/W operation complete */ |
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val = tegra_se_read_32(SE0_INT_STATUS_REG_OFFSET); |
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if (SE0_INT_OP_DONE(val) == SE0_INT_OP_DONE_CLEAR) { |
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ERROR("%s: Engine busy state too many times! val = 0x%x\n", |
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__func__, val); |
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return -ETIMEDOUT; |
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} |
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/* Read SE0 status idle to ensure H/W operation complete */ |
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val = tegra_se_read_32(SE0_SHA_STATUS_0); |
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if (val != SE0_SHA_STATUS_IDLE) { |
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ERROR("%s: Idle state timeout! val = 0x%x\n", __func__, |
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val); |
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return -ETIMEDOUT; |
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} |
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/* Ensure that no errors are thrown during operation */ |
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val = tegra_se_read_32(SE0_ERR_STATUS_REG_OFFSET); |
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if (val != SE0_ERR_STATUS_CLEAR) { |
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ERROR("%s: Error during SE operation! val = 0x%x", |
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__func__, val); |
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return -ENOTSUP; |
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} |
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return 0; |
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} |
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/*
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* Security engine primitive normal operations |
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*/ |
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static int32_t tegra_se_start_normal_operation(uint64_t src_addr, |
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uint32_t nbytes, uint32_t last_buf, uint32_t src_len_inbytes) |
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{ |
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int32_t ret = 0; |
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uint32_t val = 0U; |
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uint32_t src_in_lo; |
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uint32_t src_in_msb; |
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uint32_t src_in_hi; |
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if ((src_addr == 0UL) || (nbytes == 0U)) |
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return -EINVAL; |
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src_in_lo = (uint32_t)src_addr; |
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src_in_msb = ((uint32_t)(src_addr >> 32U) & 0xffU); |
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src_in_hi = ((src_in_msb << SE0_IN_HI_ADDR_HI_0_MSB_SHIFT) | |
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(nbytes & 0xffffffU)); |
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/* set SRC_IN_ADDR_LO and SRC_IN_ADDR_HI*/ |
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tegra_se_write_32(SE0_IN_ADDR, src_in_lo); |
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tegra_se_write_32(SE0_IN_HI_ADDR_HI, src_in_hi); |
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val = tegra_se_read_32(SE0_INT_STATUS_REG_OFFSET); |
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if (val > 0U) { |
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tegra_se_write_32(SE0_INT_STATUS_REG_OFFSET, 0x00000U); |
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} |
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/* Enable SHA interrupt for SE0 Operation */ |
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tegra_se_write_32(SE0_SHA_INT_ENABLE, 0x1aU); |
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/* flush to DRAM for SE to use the updated contents */ |
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flush_dcache_range(src_addr, src_len_inbytes); |
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/* Start SHA256 operation */ |
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if (last_buf == 1U) { |
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tegra_se_write_32(SE0_OPERATION_REG_OFFSET, SE0_OP_START | |
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SE0_UNIT_OPERATION_PKT_LASTBUF_FIELD); |
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} else { |
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tegra_se_write_32(SE0_OPERATION_REG_OFFSET, SE0_OP_START); |
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} |
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/* Wait for SE-operation to finish */ |
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udelay(SE0_MAX_BUSY_TIMEOUT_MS * 100U); |
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/* Check SE0 operation status */ |
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ret = tegra_se_operation_complete(); |
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if (ret != 0) { |
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ERROR("SE operation complete Failed! 0x%x", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int32_t tegra_se_calculate_sha256_hash(uint64_t src_addr, |
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uint32_t src_len_inbyte) |
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{ |
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uint32_t val, last_buf, i; |
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int32_t ret = 0; |
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uint32_t operations; |
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uint64_t src_len_inbits; |
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uint32_t len_bits_msb; |
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uint32_t len_bits_lsb; |
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uint32_t number_of_operations, max_bytes, bytes_left, remaining_bytes; |
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if (src_len_inbyte > MAX_SHA_ENGINE_CHUNK_SIZE) { |
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ERROR("SHA input chunk size too big: 0x%x\n", src_len_inbyte); |
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return -EINVAL; |
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} |
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if (src_addr == 0UL) { |
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return -EINVAL; |
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} |
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/* number of bytes per operation */ |
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max_bytes = SHA256_HASH_SIZE_BYTES * SHA256_MSG_LENGTH_ONETIME; |
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src_len_inbits = src_len_inbyte * 8U; |
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len_bits_msb = (uint32_t)(src_len_inbits >> 32U); |
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len_bits_lsb = (uint32_t)(src_len_inbits & 0xFFFFFFFF); |
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/* program SE0_CONFIG for SHA256 operation */ |
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val = SE0_CONFIG_ENC_ALG_SHA | SE0_CONFIG_ENC_MODE_SHA256 | |
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SE0_CONFIG_DEC_ALG_NOP | SE0_CONFIG_DST_HASHREG; |
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tegra_se_write_32(SE0_SHA_CONFIG, val); |
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/* set SE0_SHA_MSG_LENGTH registers */ |
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tegra_se_write_32(SE0_SHA_MSG_LENGTH_0, len_bits_lsb); |
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tegra_se_write_32(SE0_SHA_MSG_LEFT_0, len_bits_lsb); |
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tegra_se_write_32(SE0_SHA_MSG_LENGTH_1, len_bits_msb); |
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/* zero out unused SE0_SHA_MSG_LENGTH and SE0_SHA_MSG_LEFT */ |
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tegra_se_write_32(SE0_SHA_MSG_LENGTH_2, 0U); |
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tegra_se_write_32(SE0_SHA_MSG_LENGTH_3, 0U); |
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tegra_se_write_32(SE0_SHA_MSG_LEFT_1, 0U); |
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tegra_se_write_32(SE0_SHA_MSG_LEFT_2, 0U); |
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tegra_se_write_32(SE0_SHA_MSG_LEFT_3, 0U); |
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number_of_operations = src_len_inbyte / max_bytes; |
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remaining_bytes = src_len_inbyte % max_bytes; |
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if (remaining_bytes > 0U) { |
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number_of_operations += 1U; |
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} |
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/*
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* 1. Operations == 1: program SE0_SHA_TASK register to initiate SHA256 |
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* hash generation by setting |
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* 1(SE0_SHA_CONFIG_HW_INIT_HASH) to SE0_SHA_TASK |
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* and start SHA256-normal operation. |
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* 2. 1 < Operations < number_of_operations: program SE0_SHA_TASK to |
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* 0(SE0_SHA_CONFIG_HW_INIT_HASH_DISABLE) to load |
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* intermediate SHA256 digest result from |
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* HASH_RESULT register to continue SHA256 |
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* generation and start SHA256-normal operation. |
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* 3. Operations == number_of_operations: continue with step 2 and set |
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* max_bytes to bytes_left to process final |
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* hash-result generation and |
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* start SHA256-normal operation. |
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*/ |
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bytes_left = src_len_inbyte; |
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for (operations = 1U; operations <= number_of_operations; |
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operations++) { |
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if (operations == SHA_FIRST_OP) { |
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val = SE0_SHA_CONFIG_HW_INIT_HASH; |
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} else { |
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/* Load intermediate SHA digest result to
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* SHA:HASH_RESULT(0..7) to continue the SHA |
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* calculation and tell the SHA engine to use it. |
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*/ |
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for (i = 0U; (i / BYTES_IN_WORD) <= |
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SHA256_MAX_HASH_RESULT; i += BYTES_IN_WORD) { |
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val = tegra_se_read_32(SE0_SHA_HASH_RESULT_0 + |
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i); |
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tegra_se_write_32(SE0_SHA_HASH_RESULT_0 + i, |
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val); |
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} |
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val = SE0_SHA_CONFIG_HW_INIT_HASH_DISABLE; |
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if (len_bits_lsb <= (max_bytes * 8U)) { |
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len_bits_lsb = (remaining_bytes * 8U); |
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} else { |
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len_bits_lsb -= (max_bytes * 8U); |
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} |
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tegra_se_write_32(SE0_SHA_MSG_LEFT_0, len_bits_lsb); |
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} |
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tegra_se_write_32(SE0_SHA_TASK_CONFIG, val); |
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max_bytes = (SHA256_HASH_SIZE_BYTES * |
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SHA256_MSG_LENGTH_ONETIME); |
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if (bytes_left < max_bytes) { |
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max_bytes = bytes_left; |
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last_buf = 1U; |
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} else { |
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bytes_left = bytes_left - max_bytes; |
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last_buf = 0U; |
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} |
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/* start operation */ |
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ret = tegra_se_start_normal_operation(src_addr, max_bytes, |
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last_buf, src_len_inbyte); |
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if (ret != 0) { |
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ERROR("Error during SE operation! 0x%x", ret); |
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return -EINVAL; |
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} |
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} |
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return ret; |
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} |
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/*
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* Handler to generate SHA256 and save SHA256 hash to PMC-Scratch register. |
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*/ |
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int32_t tegra_se_save_sha256_hash(uint64_t bl31_base, uint32_t src_len_inbyte) |
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{ |
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int32_t ret = 0; |
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uint32_t val = 0U, hash_offset = 0U, scratch_offset = 0U, security; |
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/*
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* Set SE_SOFT_SETTINGS=SE_SECURE to prevent NS process to change SE |
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* registers. |
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*/ |
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security = tegra_se_read_32(SE0_SECURITY); |
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tegra_se_write_32(SE0_SECURITY, security | SE0_SECURITY_SE_SOFT_SETTING); |
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ret = tegra_se_calculate_sha256_hash(bl31_base, src_len_inbyte); |
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if (ret != 0L) { |
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ERROR("%s: SHA256 generation failed\n", __func__); |
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return ret; |
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} |
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/*
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* Reset SE_SECURE to previous value. |
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*/ |
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tegra_se_write_32(SE0_SECURITY, security); |
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/* read SHA256_HASH_RESULT and save to PMC Scratch registers */ |
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scratch_offset = SECURE_SCRATCH_TZDRAM_SHA256_HASH_START; |
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while (scratch_offset <= SECURE_SCRATCH_TZDRAM_SHA256_HASH_END) { |
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val = tegra_se_read_32(SE0_SHA_HASH_RESULT_0 + hash_offset); |
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mmio_write_32(TEGRA_SCRATCH_BASE + scratch_offset, val); |
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hash_offset += BYTES_IN_WORD; |
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scratch_offset += BYTES_IN_WORD; |
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} |
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return ret; |
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} |
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@ -0,0 +1,100 @@ |
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/*
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef SE_PRIVATE_H |
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#define SE_PRIVATE_H |
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#include <lib/utils_def.h> |
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/* SE0 security register */ |
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#define SE0_SECURITY U(0x18) |
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#define SE0_SECURITY_SE_SOFT_SETTING (((uint32_t)1) << 16U) |
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/* SE0 config register */ |
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#define SE0_SHA_CONFIG U(0x104) |
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#define SE0_SHA_TASK_CONFIG U(0x108) |
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#define SE0_SHA_CONFIG_HW_INIT_HASH ((1U) << 0U) |
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#define SE0_SHA_CONFIG_HW_INIT_HASH_DISABLE U(0) |
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#define SE0_CONFIG_ENC_ALG_SHIFT U(12) |
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#define SE0_CONFIG_ENC_ALG_SHA \ |
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(((uint32_t)3) << SE0_CONFIG_ENC_ALG_SHIFT) |
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#define SE0_CONFIG_DEC_ALG_SHIFT U(8) |
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#define SE0_CONFIG_DEC_ALG_NOP \ |
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(((uint32_t)0) << SE0_CONFIG_DEC_ALG_SHIFT) |
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#define SE0_CONFIG_DST_SHIFT U(2) |
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#define SE0_CONFIG_DST_HASHREG \ |
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(((uint32_t)1) << SE0_CONFIG_DST_SHIFT) |
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#define SHA256_HASH_SIZE_BYTES U(256) |
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#define SE0_CONFIG_ENC_MODE_SHIFT U(24) |
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#define SE0_CONFIG_ENC_MODE_SHA256 \ |
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(((uint32_t)5) << SE0_CONFIG_ENC_MODE_SHIFT) |
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/* SHA input message length */ |
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#define SE0_SHA_MSG_LENGTH_0 U(0x11c) |
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#define SE0_SHA_MSG_LENGTH_1 U(0x120) |
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#define SE0_SHA_MSG_LENGTH_2 U(0x124) |
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#define SE0_SHA_MSG_LENGTH_3 U(0x128) |
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/* SHA input message left */ |
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#define SE0_SHA_MSG_LEFT_0 U(0x12c) |
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#define SE0_SHA_MSG_LEFT_1 U(0x130) |
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#define SE0_SHA_MSG_LEFT_2 U(0x134) |
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#define SE0_SHA_MSG_LEFT_3 U(0x138) |
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/* SE Hash Result */ |
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#define SE0_SHA_HASH_RESULT_0 U(0x13c) |
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/* SE OPERATION */ |
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#define SE0_OPERATION_REG_OFFSET U(0x17c) |
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#define SE0_UNIT_OPERATION_PKT_LASTBUF_SHIFT U(16) |
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#define SE0_UNIT_OPERATION_PKT_LASTBUF_FIELD \ |
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(((uint32_t)0x1) << SE0_UNIT_OPERATION_PKT_LASTBUF_SHIFT) |
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#define SE0_OPERATION_SHIFT U(0) |
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#define SE0_OP_START \ |
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(((uint32_t)0x1) << SE0_OPERATION_SHIFT) |
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/* SE Interrupt */ |
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#define SE0_SHA_INT_ENABLE U(0x180) |
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#define SE0_INT_STATUS_REG_OFFSET U(0x184) |
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#define SE0_INT_OP_DONE_SHIFT U(4) |
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#define SE0_INT_OP_DONE_CLEAR \ |
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(((uint32_t)0) << SE0_INT_OP_DONE_SHIFT) |
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#define SE0_INT_OP_DONE(x) \ |
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((x) & (((uint32_t)0x1) << SE0_INT_OP_DONE_SHIFT)) |
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/* SE SHA status */ |
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#define SE0_SHA_STATUS_0 U(0x188) |
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#define SE0_SHA_STATUS_IDLE U(0) |
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/* SE error status */ |
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#define SE0_ERR_STATUS_REG_OFFSET U(0x18c) |
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#define SE0_ERR_STATUS_CLEAR U(0) |
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#define SE0_IN_ADDR U(0x10c) |
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#define SE0_IN_HI_ADDR_HI U(0x110) |
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#define SE0_IN_HI_ADDR_HI_0_MSB_SHIFT U(24) |
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/* SE error status */ |
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#define SECURE_SCRATCH_TZDRAM_SHA256_HASH_START SECURE_SCRATCH_RSV63_LO |
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#define SECURE_SCRATCH_TZDRAM_SHA256_HASH_END SECURE_SCRATCH_RSV66_HI |
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/*******************************************************************************
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* Inline functions definition |
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******************************************************************************/ |
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static inline uint32_t tegra_se_read_32(uint32_t offset) |
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{ |
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return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset)); |
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} |
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static inline void tegra_se_write_32(uint32_t offset, uint32_t val) |
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{ |
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mmio_write_32(((uint32_t)(TEGRA_SE0_BASE + offset)), val); |
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} |
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#endif /* SE_PRIVATE_H */ |
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