From 66bf3ba482e46137e19f368f1386436a33eaba74 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 28 Feb 2023 16:21:51 -0600 Subject: [PATCH] fix(cpus): workaround for Cortex-A78C erratum 2779484 Cortex-A78C erratum 2779484 is a Cat B erratum that applies to revisions r0p1 and r0p2 and is still open. The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this bit might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN2004089/latest Signed-off-by: Bipin Ravi Change-Id: I9a8c16a845c3ba6eb2f17a5119aa6ca09a0d27ed --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/cortex_a78c.h | 7 ++++- lib/cpus/aarch64/cortex_a78c.S | 36 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++ 4 files changed, 54 insertions(+), 1 deletion(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 53b54b8b6..0f6277860 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -369,6 +369,10 @@ For Cortex-A78C, the following errata build flags are defined : Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. This erratum is still open. +- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to + Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. + This erratum is still open. + For Cortex-X1 CPU, the following errata build flags are defined: - ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h index 35e543c17..18cba2c0b 100644 --- a/include/lib/cpus/aarch64/cortex_a78c.h +++ b/include/lib/cpus/aarch64/cortex_a78c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,6 +33,11 @@ #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2 + /******************************************************************************* * CPU Implementation Specific Selected Instruction registers ******************************************************************************/ diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index 5cdce89c2..71f07258b 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -177,6 +177,36 @@ func check_errata_2772121 b cpu_rev_var_ls endfunc check_errata_2772121 +/* -------------------------------------------------- + * Errata Workaround for Cortex A78C Errata 2779484. + * This applies to revisions r0p1 and r0p2. + * It is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_a78c_2779484_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2779484 + cbz x0, 1f + + /* Apply the workaround */ + mrs x1, CORTEX_A78C_ACTLR3_EL1 + orr x1, x1, #BIT(47) + msr CORTEX_A78C_ACTLR3_EL1, x1 + +1: + ret x17 +endfunc errata_a78c_2779484_wa + +func check_errata_2779484 + /* Applies to r0p1 and r0p2*/ + mov x1, #0x01 + mov x2, #0x02 + b cpu_rev_var_range +endfunc check_errata_2779484 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -215,6 +245,11 @@ func cortex_a78c_reset_func bl errata_a78c_2395411_wa #endif +#if ERRATA_A78C_2779484 + mov x0, x18 + bl errata_a78c_2779484_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-A78c generic vectors are overridden to apply errata @@ -269,6 +304,7 @@ func cortex_a78c_errata_report report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749 report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411 report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121 + report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 112d8cba8..0f10061a1 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -407,6 +407,10 @@ ERRATA_A78C_2395411 ?=0 # applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open. ERRATA_A78C_2772121 ?=0 +# Flag to apply erratum 2779484 workaround during reset. This erratum +# applies to revisions r0p1 and r0p2 of the A78C cpu. It is still open. +ERRATA_A78C_2779484 ?=0 + # Flag to apply erratum 1821534 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1. ERRATA_X1_1821534 ?=0 @@ -1097,6 +1101,10 @@ $(eval $(call add_define,ERRATA_A78C_2395411)) $(eval $(call assert_boolean,ERRATA_A78C_2772121)) $(eval $(call add_define,ERRATA_A78C_2772121)) +# Process ERRATA_A78C_2779484 flag +$(eval $(call assert_boolean,ERRATA_A78C_2779484)) +$(eval $(call add_define,ERRATA_A78C_2779484)) + # Process ERRATA_X1_1821534 flag $(eval $(call assert_boolean,ERRATA_X1_1821534)) $(eval $(call add_define,ERRATA_X1_1821534))