feat(cpus): support to update External LLC presence in Neoverse N3

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with the build option 'NEOVERSE_Nx_EXTERNAL_LLC'.

Change-Id: I2567283a55c0d6e2f9fd986b7dbab91c7a815d3d
Signed-off-by: Younghyun Park <younghyunpark@google.com>

include/lib/cpus/aarch64/neoverse_n3.h

@@ -13,6 +13,7 @@
  * CPU Extended Control register specific definitions
  ******************************************************************************/
 #define NEOVERSE_N3_CPUECTLR_EL1			S3_0_C15_C1_4
+#define NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT		(ULL(1) << 0)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions

lib/cpus/aarch64/neoverse_n3.S

@@ -24,6 +24,11 @@
 cpu_reset_func_start neoverse_n3
 	/* Disable speculative loads */
 	msr	SSBS, xzr
+
+#if NEOVERSE_Nx_EXTERNAL_LLC
+	/* Some systems may have External LLC, core needs to be made aware */
+	sysreg_bit_set NEOVERSE_N3_CPUECTLR_EL1, NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT
+#endif
 cpu_reset_func_end neoverse_n3
 
 	/* ----------------------------------------------------