From 7285fd5f9aa6d9cc0e0f1dc9c71785b46a88d999 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Thu, 10 Jun 2021 15:22:48 +0100 Subject: [PATCH] feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1 For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode. The underlying changes for enabling PIE in aarch32 is submitted in commit 4324a14bf Signed-off-by: Manish Pandey Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469 --- docs/plat/arm/fvp/index.rst | 8 ++++---- include/plat/arm/common/arm_def.h | 12 ++++++++---- plat/arm/board/fvp/include/platform_def.h | 6 ++++++ plat/arm/common/arm_common.mk | 6 +++--- plat/arm/common/sp_min/arm_sp_min_setup.c | 2 ++ 5 files changed, 23 insertions(+), 11 deletions(-) diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 8e46083e8..710043ee6 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -526,8 +526,8 @@ with 8 CPUs using the AArch64 build of TF-A. Notes: -- If Position Independent Executable (PIE) support is enabled for BL31 - in this config, it can be loaded at any valid address for execution. +- Position Independent Executable (PIE) support is enabled in this + config allowing BL31 to be loaded at any valid address for execution. - Since a FIP is not loaded when using BL31 as reset entrypoint, the ``--data=""@`` @@ -588,8 +588,8 @@ with 8 CPUs using the AArch32 build of TF-A. --data cluster0.cpu0="/"@0x84000000 .. note:: - The load address of ```` depends on the value ``BL32_BASE``. - It should match the address programmed into the RVBAR register as well. + Position Independent Executable (PIE) support is enabled in this + config allowing SP_MIN to be loaded at any valid address for execution. Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 00746c6da..ae80628f1 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -465,12 +465,16 @@ * BL32 specific defines for EL3 runtime in AArch32 mode ******************************************************************************/ # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +# if !ENABLE_PIE +# error "BL32 must be a PIE if RESET_TO_SP_MIN=1." +#endif /* - * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding - * the page reserved for fw_configs) to BL32 + * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely + * used for building BL32 and not used for loading BL32. */ -# define BL32_BASE ARM_FW_CONFIGS_LIMIT -# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +# define BL32_BASE 0x0 +# define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE # else /* Put BL32 below BL2 in the Trusted SRAM.*/ # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index c46ddbe92..8b25a5463 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -150,12 +150,18 @@ #endif /* RESET_TO_BL31 */ #ifndef __aarch64__ +#if RESET_TO_SP_MIN +/* Size of Trusted SRAM - the first 4KB of shared memory */ +#define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) +#else /* * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is * calculated using the current SP_MIN PROGBITS debug size plus the sizes of * BL2 and BL1-RW */ # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) +#endif /* RESET_TO_SP_MIN */ #endif /* diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 5faf9f907..f1e4cf505 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -154,9 +154,9 @@ ARM_CRYPTOCELL_INTEG := 0 $(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG)) $(eval $(call add_define,ARM_CRYPTOCELL_INTEG)) -# Enable PIE support for RESET_TO_BL31 case -ifeq (${RESET_TO_BL31},1) - ENABLE_PIE := 1 +# Enable PIE support for RESET_TO_BL31/RESET_TO_SP_MIN case +ifneq ($(filter 1,${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) + ENABLE_PIE := 1 endif # CryptoCell integration relies on coherent buffers for passing data from diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c index 270093c4e..f15c13791 100644 --- a/plat/arm/common/sp_min/arm_sp_min_setup.c +++ b/plat/arm/common/sp_min/arm_sp_min_setup.c @@ -32,7 +32,9 @@ static entry_point_info_t bl33_image_ep_info; * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. */ +#if !RESET_TO_SP_MIN CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows); +#endif /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for the