Merge changes from topic "mtk_spm" into integration

* changes:
  refactor(mediatek): add new LPM API for further extension
  refactor(mediatek): change the parameters of LPM API
  refactor(mediatek): change LPM header file path for further extension
  feat(mt8188): keep infra and peri on when system suspend
  feat(mt8188): enable SPM and LPM
  feat(mt8188): add SPM feature support
  feat(mt8188): add MT8188 SPM support
  feat(mediatek): add SPM's SSPM notifier
  feat(mt8188): add the register definitions accessed by SPM
  feat(mediatek): add new features of LPM

plat/mediatek/build_helpers/options.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -23,3 +23,4 @@ $(eval $(call add_defined_option,CONFIG_MTK_SMP_EN))
 $(eval $(call add_defined_option,CONFIG_MTK_CPU_SUSPEND_EN))
 $(eval $(call add_defined_option,CONFIG_MTK_PM_ARCH))
 $(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_ARCH))
+$(eval $(call add_defined_option,CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND))

plat/mediatek/common/lpm/mt_lp_api.c

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lpm/mt_lp_api.h>
+
+int mt_audio_update(int type)
+{
+	int ret, val;
+
+	switch (type) {
+	case AUDIO_AFE_ENTER:
+	case AUDIO_AFE_LEAVE:
+		val = (type == AUDIO_AFE_ENTER) ? 1 : 0;
+		ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_FMAUDIO, &val);
+		break;
+	case AUDIO_DSP_ENTER:
+	case AUDIO_DSP_LEAVE:
+		val = (type == AUDIO_DSP_ENTER) ? 1 : 0;
+		ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_ADSP, &val);
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+int mtk_usb_update(int type)
+{
+	int ret, val;
+
+	switch (type) {
+	case LPM_USB_ENTER:
+	case LPM_USB_LEAVE:
+		val = (type == LPM_USB_ENTER) ? 1 : 0;
+		ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_USB_INFRA, &val);
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}

plat/mediatek/common/lpm/mt_lp_rm.c

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <mt_lp_rm.h>
 #include <stddef.h>
+#include <lpm/mt_lp_rm.h>
 
 struct platform_mt_resource_manager {
 	unsigned int count;
@@ -36,12 +36,11 @@ int mt_lp_rm_register(struct mt_resource_manager *rm)
 	return MT_RM_STATUS_OK;
 }
 
-int mt_lp_rm_reset_constraint(int idx, unsigned int cpuid, int stateid)
+int mt_lp_rm_reset_constraint(unsigned int idx, unsigned int cpuid, int stateid)
 {
 	struct mt_resource_constraint const *rc = NULL;
 
-	if ((plat_mt_rm.plat_rm == NULL) || (idx < 0) ||
-	    (idx >= plat_mt_rm.count)) {
+	if ((plat_mt_rm.plat_rm == NULL) || (idx >= plat_mt_rm.count)) {
 		return MT_RM_STATUS_BAD;
 	}
 
@@ -54,39 +53,92 @@ int mt_lp_rm_reset_constraint(int idx, unsigned int cpuid, int stateid)
 	return rc->reset(cpuid, stateid);
 }
 
-int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
-				     int stateid, void *priv)
+int mt_lp_rm_get_status(unsigned int type, void *priv)
+{
+	int res = 0;
+	struct mt_resource_constraint *const *con;
+	struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
+
+	if ((rm == NULL) || (type >= PLAT_RC_MAX)) {
+		return -1;
+	}
+
+	for (con = rm->consts; *con != NULL; con++) {
+		if ((*con)->get_status == NULL) {
+			continue;
+		}
+		res = (*con)->get_status(type, priv);
+		if (res == MT_RM_STATUS_STOP) {
+			break;
+		}
+	}
+
+	return res;
+}
+
+int mt_lp_rm_do_constraint(unsigned int constraint_id, unsigned int cpuid, int stateid)
+{
+	int res = MT_RM_STATUS_BAD;
+	struct mt_resource_constraint const *rc;
+	struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
+
+	if ((rm == NULL) || (constraint_id >= plat_mt_rm.count)) {
+		return res;
+	}
+
+	rc = rm->consts[constraint_id];
+	if ((rc != NULL) && (rc->run != NULL)) {
+		res = rc->run(cpuid, stateid);
+	}
+
+	return res;
+}
+
+int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid,
+			     int stateid, void *priv)
 {
-	int i, res = MT_RM_STATUS_BAD;
+	unsigned int i;
+	int res = MT_RM_STATUS_BAD;
 	struct mt_resource_constraint *const *rc;
 	struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
 
-	if ((rm == NULL) || (idx < 0) || (idx >= plat_mt_rm.count)) {
+	if ((rm == NULL) || (idx >= plat_mt_rm.count)) {
 		return res;
 	}
 
 	/* If subsys clk/mtcmos is on, add block-resource-off flag */
 	if (rm->update != NULL) {
-		res = rm->update(rm->consts, stateid, priv);
+		res = rm->update(rm->consts, plat_mt_rm.count, stateid, priv);
 		if (res != 0) {
-			return res;
+			return MT_RM_STATUS_BAD;
 		}
 	}
 
+	res = MT_RM_STATUS_BAD;
 	for (i = idx, rc = (rm->consts + idx); *rc != NULL; i++, rc++) {
 		if (((*rc)->is_valid != NULL) &&
 		    ((*rc)->is_valid(cpuid, stateid))) {
-			if (((*rc)->run != NULL) &&
-			    ((*rc)->run(cpuid, stateid) == 0)) {
-				res = i;
-				break;
-			}
+			res = i;
+			break;
 		}
 	}
 
 	return res;
 }
 
+int mt_lp_rm_find_and_run_constraint(unsigned int idx, unsigned int cpuid,
+				     int stateid, void *priv)
+{
+	int res = MT_RM_STATUS_BAD;
+
+	res = mt_lp_rm_find_constraint(idx, cpuid, stateid, priv);
+	if (res != MT_RM_STATUS_BAD) {
+		mt_lp_rm_do_constraint(res, cpuid, stateid);
+	}
+
+	return res;
+}
+
 int mt_lp_rm_do_update(int stateid, int type, void const *p)
 {
 	int res = MT_RM_STATUS_BAD;

plat/mediatek/common/lpm/mt_lp_rm.h

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef MT_LP_RM_H
-#define MT_LP_RM_H
-
-#include <stdbool.h>
-
-#define MT_RM_STATUS_OK		0
-#define MT_RM_STATUS_BAD	-1
-
-enum PLAT_MT_LPM_RC_TYPE {
-	PLAT_RC_UPDATE_CONDITION,
-	PLAT_RC_UPDATE_REMAIN_IRQS
-};
-
-struct mt_resource_constraint {
-	int level;
-	int (*init)(void);
-	bool (*is_valid)(unsigned int cpu, int stateid);
-	int (*update)(int stateid, int type, const void *p);
-	int (*run)(unsigned int cpu, int stateid);
-	int (*reset)(unsigned int cpu, int stateid);
-	unsigned int (*allow)(int stateid);
-};
-
-struct mt_resource_manager {
-	int (*update)(struct mt_resource_constraint **con,
-		      int stateid, void *priv);
-	struct mt_resource_constraint **consts;
-};
-
-extern int mt_lp_rm_register(struct mt_resource_manager *rm);
-extern int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
-					    int stateid, void *priv);
-extern int mt_lp_rm_reset_constraint(int constraint_id, unsigned int cpuid,
-				     int stateid);
-extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
-#endif /* MT_LP_RM_H */

plat/mediatek/common/lpm/mt_lp_rq.c

@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/spinlock.h>
+#include <lpm/mt_lp_rqm.h>
+
+struct mt_lp_res_req_m {
+	unsigned int uname[MT_LP_RQ_USER_MAX];
+	unsigned int user_num;
+	unsigned int user_valid;
+	unsigned int resource_num;
+	unsigned int generic_resource_req;
+	unsigned int flag;
+	struct mt_resource_req_manager *plat_rqm;
+};
+
+static struct mt_lp_res_req_m plat_mt_rqm;
+static spinlock_t mt_lp_rq_lock;
+
+static int mt_lp_resource_request(struct mt_lp_resource_user *this, unsigned int resource)
+{
+	int i;
+	struct mt_lp_res_req *const *rs;
+
+	if ((this == NULL) || (resource == 0) || (resource > MT_LP_RQ_ALL)) {
+		ERROR("invalid request(%x)\n", resource);
+		return MT_LP_RQ_STA_BAD;
+	}
+
+	spin_lock(&mt_lp_rq_lock);
+
+	rs = (plat_mt_rqm.plat_rqm)->res;
+	for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+		if ((resource & rs[i]->res_id) != 0) {
+			rs[i]->res_usage |= this->umask;
+		}
+	}
+
+	plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+	spin_unlock(&mt_lp_rq_lock);
+
+	return MT_LP_RQ_STA_OK;
+}
+
+static int mt_lp_resource_release(struct mt_lp_resource_user *this)
+{
+	int i;
+	struct mt_lp_res_req *const *rs;
+
+	if (this == NULL) {
+		return MT_LP_RQ_STA_BAD;
+	}
+
+	spin_lock(&mt_lp_rq_lock);
+
+	rs = (plat_mt_rqm.plat_rqm)->res;
+	for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+		rs[i]->res_usage &= ~(this->umask);
+	}
+
+	plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+	spin_unlock(&mt_lp_rq_lock);
+
+	return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_resource_request_manager_register(struct mt_resource_req_manager *rqm)
+{
+	unsigned int count;
+	struct mt_lp_res_req *const *rs;
+
+	if ((rqm == NULL) || (rqm->res == NULL) || (plat_mt_rqm.plat_rqm != NULL)) {
+		return MT_LP_RQ_STA_BAD;
+	}
+
+	rs = rqm->res;
+	count = 0;
+	while (*rs != NULL) {
+		count++;
+		rs++;
+	}
+
+	plat_mt_rqm.plat_rqm = rqm;
+	plat_mt_rqm.resource_num = count;
+
+	return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_resource_user_register(char *user, struct mt_lp_resource_user *ru)
+{
+	int i, len;
+	unsigned int uname;
+
+	if ((plat_mt_rqm.plat_rqm == NULL) || (plat_mt_rqm.user_num >= MT_LP_RQ_USER_MAX) ||
+	    (user == NULL)) {
+		ru->uid = MT_LP_RQ_USER_INVALID;
+		ru->umask = 0;
+		ru->request = NULL;
+		ru->release = NULL;
+		ERROR("rqm register user invalid\n");
+		return MT_LP_RQ_STA_BAD;
+	}
+
+	len = strnlen(user, MT_LP_RQ_USER_NAME_LEN);
+
+	uname = 0;
+	for (i = 0; i < len; i++) {
+		uname |= (user[i] << (MT_LP_RQ_USER_CHAR_U * i));
+	}
+
+	spin_lock(&mt_lp_rq_lock);
+	i = plat_mt_rqm.user_num;
+	plat_mt_rqm.user_num += 1;
+	plat_mt_rqm.uname[i] = uname;
+	plat_mt_rqm.user_valid |= BIT(i);
+	spin_unlock(&mt_lp_rq_lock);
+
+	ru->umask = BIT(i);
+	ru->uid = i;
+	ru->request = mt_lp_resource_request;
+	ru->release = mt_lp_resource_release;
+	INFO("%s register by %s, uid = %d\n", __func__, user, ru->uid);
+
+	return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_rq_get_status(int type, void *p)
+{
+	int i;
+	unsigned int update_sta;
+	struct mt_lp_res_req *const *rs;
+	struct resource_req_status *rq_sta = (struct resource_req_status *)p;
+
+	if (plat_mt_rqm.flag != 0) {
+		spin_lock(&mt_lp_rq_lock);
+
+		update_sta = 0;
+		rs = (plat_mt_rqm.plat_rqm)->res;
+		for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+			update_sta |= ((rs[i]->res_usage & plat_mt_rqm.user_valid) != 0) ?
+				      rs[i]->res_rq : 0;
+		}
+
+		plat_mt_rqm.generic_resource_req = update_sta;
+		plat_mt_rqm.flag = MT_LP_RQ_FLAG_DONE;
+		spin_unlock(&mt_lp_rq_lock);
+	}
+
+	switch (type) {
+	case PLAT_RQ_REQ_USAGE:
+		rs = (plat_mt_rqm.plat_rqm)->res;
+		rq_sta->val = (rq_sta->id < plat_mt_rqm.resource_num) ?
+			      rs[rq_sta->id]->res_usage : plat_mt_rqm.generic_resource_req;
+		break;
+	case PLAT_RQ_USER_NUM:
+		rq_sta->val = plat_mt_rqm.user_num;
+		break;
+	case PLAT_RQ_USER_VALID:
+		rq_sta->val = plat_mt_rqm.user_valid;
+		break;
+	case PLAT_RQ_PER_USER_NAME:
+		rq_sta->val = (rq_sta->id < plat_mt_rqm.user_num) ?
+			      plat_mt_rqm.uname[rq_sta->id] : 0;
+		break;
+	case PLAT_RQ_REQ_NUM:
+		rq_sta->val = plat_mt_rqm.resource_num;
+		break;
+	default:
+		break;
+	}
+
+	return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_rq_update_status(int type, void *p)
+{
+	unsigned int user_mask;
+	struct resource_req_status *rq_sta = (struct resource_req_status *)p;
+
+	switch (type) {
+	case PLAT_RQ_USER_VALID:
+		if (rq_sta->id < plat_mt_rqm.user_num) {
+			user_mask = BIT(rq_sta->id);
+			spin_lock(&mt_lp_rq_lock);
+			plat_mt_rqm.user_valid = (rq_sta->val == 0) ?
+						 (plat_mt_rqm.user_valid & ~(user_mask)) :
+						 (plat_mt_rqm.user_valid | user_mask);
+			plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+			spin_unlock(&mt_lp_rq_lock);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return MT_LP_RQ_STA_OK;
+}

plat/mediatek/common/lpm/rules.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -7,7 +7,10 @@
 LOCAL_DIR := $(call GET_LOCAL_DIR)
 
 MODULE := lpm
-LOCAL_SRCS-y := $(LOCAL_DIR)/mt_lp_rm.c
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/mt_lp_api.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/mt_lp_rm.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/mt_lp_rq.c
 
 PLAT_INCLUDES += -I${LOCAL_DIR}
 

plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,10 +11,10 @@
 
 #include <lib/mtk_init/mtk_init.h>
 #include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
 #include "mt_cpu_pm.h"
 #include "mt_cpu_pm_cpc.h"
 #include "mt_cpu_pm_mbox.h"
-#include <mt_lp_rm.h>
 #include "mt_smp.h"
 #include <mtk_mmap_pool.h>
 #include <platform_def.h>

plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c

@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lpm/mt_lpm_smc.h>
+#include <mt_spm.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+
+int spm_rc_condition_modifier(unsigned int id, unsigned int act,
+			      const void *val,
+			      enum mt_spm_rm_rc_type dest_rc_id,
+			      struct mt_spm_cond_tables * const tlb)
+{
+	unsigned int rc_id, cond_id, cond;
+	int res = 0;
+
+	spin_lock(&spm_lock);
+	rc_id = SPM_RC_UPDATE_COND_RC_ID_GET(id);
+	cond_id = SPM_RC_UPDATE_COND_ID_GET(id);
+
+	do {
+		if ((dest_rc_id != rc_id) || (val == NULL) || (tlb == NULL)) {
+			res = -1;
+			break;
+		}
+
+		cond = *((unsigned int *)val);
+
+		if (cond_id < PLAT_SPM_COND_MAX) {
+			if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+				SPM_RC_BITS_SET(tlb->table_cg[cond_id], cond);
+			} else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+				SPM_RC_BITS_CLR(tlb->table_cg[cond_id], cond);
+			} else {
+				res = -1;
+			}
+		} else if ((cond_id - PLAT_SPM_COND_MAX) < PLAT_SPM_COND_PLL_MAX) {
+			unsigned int pll_idx = cond_id - PLAT_SPM_COND_MAX;
+
+			cond = !!cond;
+			if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+				SPM_RC_BITS_SET(tlb->table_pll, (cond << pll_idx));
+			} else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+				SPM_RC_BITS_CLR(tlb->table_pll, (cond << pll_idx));
+			} else {
+				res = -1;
+			}
+		} else {
+			res = -1;
+		}
+	} while (0);
+
+	spin_unlock(&spm_lock);
+
+	return res;
+}
+
+int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
+				 unsigned int act,
+				 enum mt_spm_rm_rc_type dest_rc_id,
+				 struct constraint_status * const src,
+				 struct constraint_status * const dest)
+{
+	if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL) ||
+	    (src == NULL)) {
+		return -1;
+	}
+	spin_lock(&spm_lock);
+
+	switch (type) {
+	case CONSTRAINT_GET_ENTER_CNT:
+		if (id == MT_RM_CONSTRAINT_ID_ALL) {
+			dest->enter_cnt += src->enter_cnt;
+		} else {
+			dest->enter_cnt = src->enter_cnt;
+		}
+		break;
+	case CONSTRAINT_GET_VALID:
+		dest->is_valid = src->is_valid;
+		break;
+	case CONSTRAINT_COND_BLOCK:
+		dest->is_cond_block = src->is_cond_block;
+		dest->all_pll_dump = src->all_pll_dump;
+		break;
+	case CONSTRAINT_GET_COND_BLOCK_DETAIL:
+		dest->cond_res = src->cond_res;
+		break;
+	case CONSTRAINT_GET_RESIDNECY:
+		dest->residency = src->residency;
+		if (act & MT_LPM_SMC_ACT_CLR) {
+			src->residency = 0;
+		}
+		break;
+	default:
+		break;
+	}
+
+	spin_unlock(&spm_lock);
+	return 0;
+}
+
+int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
+				 unsigned int act,
+				 enum mt_spm_rm_rc_type dest_rc_id,
+				 struct constraint_status * const src,
+				 struct constraint_status * const dest)
+{
+	if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+		return -1;
+	}
+
+	spin_lock(&spm_lock);
+
+	switch (type) {
+	case CONSTRAINT_UPDATE_VALID:
+		if (src != NULL) {
+			if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+				SPM_RC_BITS_SET(dest->is_valid, src->is_valid);
+			} else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+				SPM_RC_BITS_CLR(dest->is_valid, src->is_valid);
+			}
+		}
+		break;
+	case CONSTRAINT_RESIDNECY:
+		if (act & MT_LPM_SMC_ACT_CLR) {
+			dest->residency = 0;
+		}
+		break;
+	default:
+		break;
+	}
+
+	spin_unlock(&spm_lock);
+
+	return 0;
+}
+
+int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
+				enum mt_spm_rm_rc_type dest_rc_id,
+				unsigned int valid,
+				struct constraint_status * const dest)
+{
+	if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+		return -1;
+	}
+
+	spin_lock(&spm_lock);
+	SPM_RC_BITS_SET(dest->is_valid, valid);
+	spin_unlock(&spm_lock);
+
+	return 0;
+}
+
+int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
+				enum mt_spm_rm_rc_type dest_rc_id,
+				unsigned int valid,
+				struct constraint_status * const dest)
+{
+	if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+		return -1;
+	}
+
+	spin_lock(&spm_lock);
+	SPM_RC_BITS_CLR(dest->is_valid, valid);
+	spin_unlock(&spm_lock);
+
+	return 0;
+}

plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_API_H
+#define MT_SPM_RC_API_H
+
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_internal.h>
+
+#define SPM_RC_BITS_SET(dest, src) ({ (dest) |= (src); })
+#define SPM_RC_BITS_CLR(dest, src) ({ (dest) &= (~src); })
+
+int spm_rc_condition_modifier(unsigned int id, unsigned int act,
+			      const void *val,
+			      enum mt_spm_rm_rc_type dest_rc_id,
+			      struct mt_spm_cond_tables * const tlb);
+
+int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
+				 unsigned int act,
+				 enum mt_spm_rm_rc_type dest_rc_id,
+				 struct constraint_status * const src,
+				 struct constraint_status * const dest);
+
+int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
+				 unsigned int act,
+				 enum mt_spm_rm_rc_type dest_rc_id,
+				 struct constraint_status * const src,
+				 struct constraint_status * const dest);
+
+int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
+				enum mt_spm_rm_rc_type dest_rc_id,
+				unsigned int valid,
+				struct constraint_status * const dest);
+
+int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
+				enum mt_spm_rm_rc_type dest_rc_id,
+				unsigned int valid,
+				struct constraint_status * const dest);
+
+#endif

plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c

@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#ifndef MTK_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_BUS26M_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+				 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+				 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+				 MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
+				 MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
+				 MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+				    SPM_FLAG_DISABLE_VCORE_DVS | \
+				    SPM_FLAG_DISABLE_VCORE_DFS | \
+				    SPM_FLAG_SRAM_SLEEP_CTRL | \
+				    SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
+				    SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+				    SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
+#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
+#define CONSTRAINT_BUS26M_RESOURCE_REQ	(MT_SPM_26M)
+#else
+#define CONSTRAINT_BUS26M_RESOURCE_REQ	(0)
+#endif
+
+static unsigned int bus26m_ext_opand;
+static unsigned int bus26m_ext_opand2;
+
+static struct mt_irqremain *refer2remain_irq;
+
+static struct mt_spm_cond_tables cond_bus26m = {
+	.table_cg = {
+		0xFF5DD002,	/* MTCMOS1 */
+		0x0000003C,	/* MTCMOS2 */
+		0x27AF8000,	/* INFRA0  */
+		0x22010876,	/* INFRA1  */
+		0x86000650,	/* INFRA2  */
+		0x30008020,	/* INFRA3  */
+		0x80000000,	/* INFRA4  */
+		0x01002A3B,	/* PERI0   */
+		0x00090000,	/* VPPSYS0_0  */
+		0x38FF3E69,     /* VPPSYS0_1  */
+		0xF0081450,	/* VPPSYS1_0  */
+		0x00003000,     /* VPPSYS1_1  */
+		0x00000000,	/* VDOSYS0_0  */
+		0x00000000,     /* VDOSYS0_1  */
+		0x000001FF,	/* VDOSYS1_0  */
+		0x000001E0,     /* VDOSYS1_1  */
+		0x00FB0007,	/* VDOSYS1_2  */
+	},
+	.table_pll = (PLL_BIT_UNIVPLL |
+		      PLL_BIT_MFGPLL |
+		      PLL_BIT_MSDCPLL |
+		      PLL_BIT_TVDPLL1 |
+		      PLL_BIT_TVDPLL2 |
+		      PLL_BIT_MMPLL |
+		      PLL_BIT_ETHPLL |
+		      PLL_BIT_IMGPLL |
+		      PLL_BIT_APLL1 |
+		      PLL_BIT_APLL2 |
+		      PLL_BIT_APLL3 |
+		      PLL_BIT_APLL4 |
+		      PLL_BIT_APLL5),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_BUS26M,
+	.is_valid = (MT_SPM_RC_VALID_SW |
+		     MT_SPM_RC_VALID_COND_CHECK |
+		     MT_SPM_RC_VALID_COND_LATCH |
+		     MT_SPM_RC_VALID_TRACE_TIME),
+	.is_cond_block = 0U,
+	.enter_cnt = 0U,
+	.all_pll_dump = 0U,
+	.cond_res = &cond_bus26m_res,
+	.residency = 0ULL,
+};
+
+#ifdef MTK_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+				   unsigned int irq_index,
+				   struct wake_status *wakeup)
+{
+	if ((irqs == NULL) || (wakeup == NULL)) {
+		return;
+	}
+
+	INFO("[SPM] r12=0x%08x(0x%08x), flag=0x%08x 0x%08x 0x%08x, irq:%u(0x%08x) set pending\n",
+	     wakeup->tr.comm.r12,
+	     wakeup->md32pcm_wakeup_sta,
+	     wakeup->tr.comm.debug_flag,
+	     wakeup->tr.comm.b_sw_flag0,
+	     wakeup->tr.comm.b_sw_flag1,
+	     irqs->wakeupsrc[irq_index],
+	     irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+	unsigned int idx;
+	struct wake_status *wakeup = NULL;
+	struct mt_irqremain *irqs = refer2remain_irq;
+
+	if (irqs == NULL) {
+		return;
+	}
+
+	if (spm_conservation_get_result(&wakeup) == 0) {
+		if (wakeup != NULL) {
+			for (idx = 0; idx < irqs->count; idx++) {
+				if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+				    ((wakeup->tr.comm.raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+					if ((irqs->wakeupsrc_cat[idx] &
+					     MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+						mt_spm_irq_remain_dump(irqs, idx, wakeup);
+					}
+					mt_irq_set_pending(irqs->irqs[idx]);
+				}
+			}
+		}
+	}
+}
+#endif
+
+int spm_bus26m_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+	unsigned int res_req = CONSTRAINT_BUS26M_RESOURCE_REQ;
+
+	if ((spm_lp == NULL) || (resource_req == NULL)) {
+		return -1;
+	}
+
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+
+	*resource_req |= res_req;
+	return 0;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+	return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
+		IS_MT_RM_RC_READY(status.is_valid) &&
+		(IS_PLAT_SUSPEND_ID(state_id) || (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+	const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
+	const struct mt_spm_cond_tables *tlb_check =
+		(const struct mt_spm_cond_tables *)&cond_bus26m;
+
+	if (tlb == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+						 (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+						 &cond_bus26m_res : NULL);
+	status.all_pll_dump = mt_spm_dump_all_pll(tlb, tlb_check,
+						  (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+						  &cond_bus26m_res : NULL);
+	return MT_RM_STATUS_OK;
+}
+
+static void update_rc_remain_irqs(const void *val)
+{
+	refer2remain_irq = (struct mt_irqremain *)val;
+}
+
+static void update_rc_fmaudio_adsp(int type, const void *val)
+{
+	int *flag = (int *)val;
+	unsigned int ext_op = (type == PLAT_RC_IS_ADSP) ?
+			      (MT_SPM_EX_OP_SET_IS_ADSP | MT_SPM_EX_OP_SET_SUSPEND_MODE) :
+			      MT_SPM_EX_OP_SET_SUSPEND_MODE;
+
+	if (flag == NULL) {
+		return;
+	}
+
+	if (*flag != 0) {
+		SPM_RC_BITS_SET(bus26m_ext_opand, ext_op);
+	} else {
+		SPM_RC_BITS_CLR(bus26m_ext_opand, ext_op);
+	}
+}
+
+static void update_rc_usb_peri(const void *val)
+{
+	int *flag = (int *)val;
+
+	if (flag == NULL) {
+		return;
+	}
+
+	if (*flag != 0) {
+		SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+	} else {
+		SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+	}
+}
+
+static void update_rc_usb_infra(const void *val)
+{
+	int *flag = (int *)val;
+
+	if (flag == NULL) {
+		return;
+	}
+
+	if (*flag != 0) {
+		SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+	} else {
+		SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+	}
+}
+
+static void update_rc_status(const void *val)
+{
+	const struct rc_common_state *st;
+
+	st = (const struct rc_common_state *)val;
+
+	if (st == NULL) {
+		return;
+	}
+
+	if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+		struct mt_spm_cond_tables * const tlb = &cond_bus26m;
+
+		spm_rc_condition_modifier(st->id, st->act, st->value,
+					  MT_RM_CONSTRAINT_ID_BUS26M, tlb);
+	} else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+		   (st->type == CONSTRAINT_RESIDNECY)) {
+		spm_rc_constraint_status_set(st->id, st->type, st->act,
+					     MT_RM_CONSTRAINT_ID_BUS26M,
+					     (struct constraint_status * const)st->value,
+					     (struct constraint_status * const)&status);
+	} else {
+		INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+	}
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+	int res = MT_RM_STATUS_OK;
+
+	switch (type) {
+	case PLAT_RC_UPDATE_CONDITION:
+		res = update_rc_condition(val);
+		break;
+	case PLAT_RC_UPDATE_REMAIN_IRQS:
+		update_rc_remain_irqs(val);
+		break;
+	case PLAT_RC_IS_FMAUDIO:
+	case PLAT_RC_IS_ADSP:
+		update_rc_fmaudio_adsp(type, val);
+		break;
+	case PLAT_RC_IS_USB_PERI:
+		update_rc_usb_peri(val);
+		break;
+	case PLAT_RC_IS_USB_INFRA:
+		update_rc_usb_infra(val);
+		break;
+	case PLAT_RC_STATUS:
+		update_rc_status(val);
+		break;
+	default:
+		INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+		break;
+	}
+	return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+	return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
+#endif
+	if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
+		ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+	}
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_CLR_26M_RECORD |
+				      MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      bus26m_ext_opand |
+				      bus26m_ext_opand2),
+				     CONSTRAINT_BUS26M_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_bus26m_conduct);
+	}
+	return MT_RM_STATUS_OK;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0);
+#endif
+	if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
+		ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+	}
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (bus26m_ext_opand | bus26m_ext_opand2 |
+				       MT_SPM_EX_OP_SET_WDT | ext_op),
+				      NULL);
+		bus26m_ext_opand = 0;
+	} else {
+		struct wake_status *waken = NULL;
+
+		if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+			ext_op |= MT_SPM_EX_OP_TRACE_LP;
+		}
+
+		mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+		status.enter_cnt++;
+
+		if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+			status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+		}
+	}
+
+	do_irqs_delivery();
+
+	return MT_RM_STATUS_OK;
+}
+
+int spm_get_status_rc_bus26m(unsigned int type, void *priv)
+{
+	int ret = MT_RM_STATUS_OK;
+
+	if (type == PLAT_RC_STATUS) {
+		int res = 0;
+		struct rc_common_state *st = (struct rc_common_state *)priv;
+
+		if (st == NULL) {
+			return MT_RM_STATUS_BAD;
+		}
+
+		res = spm_rc_constraint_status_get(st->id, st->type,
+						   st->act, MT_RM_CONSTRAINT_ID_BUS26M,
+						   (struct constraint_status * const)&status,
+						   (struct constraint_status * const)st->value);
+		if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+			ret = MT_RM_STATUS_STOP;
+		}
+	}
+	return ret;
+}

plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c

@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lpm_smc.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+				      SPM_FLAG_DISABLE_VCORE_DVS | \
+				      SPM_FLAG_DISABLE_VCORE_DFS | \
+				      SPM_FLAG_SRAM_SLEEP_CTRL | \
+				      SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+				      SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 (0)
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ (MT_SPM_DRAM_S1 | \
+					  MT_SPM_DRAM_S0 | \
+					  MT_SPM_SYSPLL | \
+					  MT_SPM_INFRA | \
+					  MT_SPM_26M | \
+					  MT_SPM_XO_FPM)
+
+static unsigned int cpubuckldo_status = (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_TRACE_TIME);
+static unsigned int cpubuckldo_enter_cnt;
+
+int spm_cpu_bcuk_ldo_conduct(int state_id,
+			     struct spm_lp_scen *spm_lp,
+			     unsigned int *resource_req)
+{
+	unsigned int res_req = CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+
+	if ((spm_lp == NULL) || (resource_req == NULL)) {
+		return -1;
+	}
+
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+
+	*resource_req |= res_req;
+	return 0;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+static void update_rc_status(const void *val)
+{
+	const struct rc_common_state *st = (const struct rc_common_state *)val;
+
+	if (st == NULL) {
+		return;
+	}
+
+	if ((st->type == CONSTRAINT_UPDATE_VALID) && st->value) {
+		if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
+		    (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
+			struct constraint_status *con = (struct constraint_status *)st->value;
+
+			if ((st->act & MT_LPM_SMC_ACT_CLR) > 0U) {
+				SPM_RC_BITS_CLR(cpubuckldo_status, con->is_valid);
+			} else {
+				SPM_RC_BITS_SET(cpubuckldo_status, con->is_valid);
+			}
+		}
+	}
+}
+
+int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val)
+{
+	if (type == PLAT_RC_STATUS) {
+		update_rc_status(val);
+	}
+	return MT_RM_STATUS_OK;
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+	return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	unsigned int ext_op = 0U;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : (0U)));
+#endif
+	if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
+		ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+	}
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_CLR_26M_RECORD |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				      MT_SPM_EX_OP_SET_WDT),
+				     CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_cpu_bcuk_ldo_conduct);
+	}
+
+	cpubuckldo_enter_cnt++;
+
+	return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	unsigned int ext_op = 0U;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
+		ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+	}
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+	}
+
+	return 0;
+}
+
+int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv)
+{
+	int ret = MT_RM_STATUS_OK;
+
+	if (type != PLAT_RC_STATUS) {
+		return ret;
+	}
+
+	struct rc_common_state *st = (struct rc_common_state *)priv;
+
+	if (st == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
+	    (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
+		struct constraint_status *dest;
+
+		dest = (struct constraint_status *)st->value;
+		do {
+			if (dest == NULL) {
+				break;
+			}
+			if (st->type == CONSTRAINT_GET_VALID) {
+				dest->is_valid = cpubuckldo_status;
+			} else if (st->type == CONSTRAINT_COND_BLOCK) {
+				dest->is_cond_block = 0;
+			} else if (st->type == CONSTRAINT_GET_ENTER_CNT) {
+				if (st->id == MT_RM_CONSTRAINT_ID_ALL) {
+					dest->enter_cnt += cpubuckldo_enter_cnt;
+				} else {
+					dest->enter_cnt = cpubuckldo_enter_cnt;
+				}
+			} else {
+				break;
+			}
+			if (st->id != MT_RM_CONSTRAINT_ID_ALL) {
+				ret = MT_RM_STATUS_STOP;
+			}
+		} while (0);
+	}
+	return ret;
+}

plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c

@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_DRAM_ALLOW (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+			       MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+			       MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+				  SPM_FLAG_DISABLE_VCORE_DVS | \
+				  SPM_FLAG_DISABLE_VCORE_DFS | \
+				  SPM_FLAG_SRAM_SLEEP_CTRL | \
+				  SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+				  SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1 (0)
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+	.table_cg = {
+		0xFF5DD002,	/* MTCMOS1 */
+		0x0000003C,	/* MTCMOS2 */
+		0x27AF8000,	/* INFRA0  */
+		0x20010876,	/* INFRA1  */
+		0x86000640,	/* INFRA2  */
+		0x00000000,	/* INFRA3  */
+		0x80000000,	/* INFRA4  */
+		0x01002A00,	/* PERI0   */
+		0x00080000,	/* VPPSYS0_0  */
+		0x38803000,     /* VPPSYS0_1  */
+		0x00081450,	/* VPPSYS1_0  */
+		0x00003000,     /* VPPSYS1_1  */
+		0x00000000,	/* VDOSYS0_0  */
+		0x00000000,     /* VDOSYS0_1  */
+		0x000001F8,	/* VDOSYS1_0  */
+		0x000001E0,     /* VDOSYS1_1  */
+		0x00FB0007,	/* VDOSYS1_2  */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_DRAM,
+	.is_valid = (MT_SPM_RC_VALID_SW |
+		     MT_SPM_RC_VALID_COND_CHECK |
+		     MT_SPM_RC_VALID_COND_LATCH |
+		     MT_SPM_RC_VALID_XSOC_BBLPM |
+		     MT_SPM_RC_VALID_TRACE_TIME),
+	.is_cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_dram_res,
+	.residency = 0ULL,
+};
+
+static unsigned short ext_status_dram;
+
+int spm_dram_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+	unsigned int res_req = CONSTRAINT_DRAM_RESOURCE_REQ;
+
+	if ((spm_lp == NULL) || (resource_req == NULL)) {
+		return -1;
+	}
+
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+
+	*resource_req |= res_req;
+	return 0;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+	return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK)) &&
+		IS_MT_RM_RC_READY(status.is_valid) &&
+		(IS_PLAT_SUSPEND_ID(state_id) ||
+		 (state_id == MT_PLAT_PWR_STATE_SYSTEM_MEM) ||
+		 (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
+		 (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+	const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
+	const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+
+	if (tlb == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+						 (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+						  &cond_dram_res : NULL);
+	return MT_RM_STATUS_OK;
+}
+
+static void update_rc_clkbuf_status(const void *val)
+{
+	unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
+
+	if (is_flight != 0U) {
+		spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
+					    MT_RM_CONSTRAINT_ID_DRAM,
+					    MT_SPM_RC_VALID_FLIGHTMODE,
+					    (struct constraint_status * const)&status);
+	} else {
+		spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
+					    MT_RM_CONSTRAINT_ID_DRAM,
+					    MT_SPM_RC_VALID_FLIGHTMODE,
+					    (struct constraint_status * const)&status);
+	}
+}
+
+static void update_rc_ufs_status(const void *val)
+{
+	unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
+
+	if (is_ufs_h8 != 0U) {
+		spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
+					    MT_RM_CONSTRAINT_ID_DRAM,
+					    MT_SPM_RC_VALID_UFS_H8,
+					    (struct constraint_status * const)&status);
+	} else {
+		spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
+					    MT_RM_CONSTRAINT_ID_DRAM,
+					    MT_SPM_RC_VALID_UFS_H8,
+					    (struct constraint_status * const)&status);
+	}
+}
+
+static void update_rc_status(const void *val)
+{
+	const struct rc_common_state *st;
+
+	st = (const struct rc_common_state *)val;
+
+	if (st == NULL) {
+		return;
+	}
+
+	if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+		struct mt_spm_cond_tables * const tlb = &cond_dram;
+
+		spm_rc_condition_modifier(st->id, st->act, st->value,
+					  MT_RM_CONSTRAINT_ID_DRAM, tlb);
+	} else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+		   (st->type == CONSTRAINT_RESIDNECY)) {
+		spm_rc_constraint_status_set(st->id, st->type, st->act,
+					     MT_RM_CONSTRAINT_ID_DRAM,
+					     (struct constraint_status * const)st->value,
+					     (struct constraint_status * const)&status);
+	} else {
+		INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+	}
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+	int res = MT_RM_STATUS_OK;
+
+	switch (type) {
+	case PLAT_RC_UPDATE_CONDITION:
+		res = update_rc_condition(val);
+		break;
+	case PLAT_RC_CLKBUF_STATUS:
+		update_rc_clkbuf_status(val);
+		break;
+	case PLAT_RC_UFS_STATUS:
+		update_rc_ufs_status(val);
+		break;
+	case PLAT_RC_STATUS:
+		update_rc_status(val);
+		break;
+	default:
+		INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+		break;
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+	return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	ext_status_dram = status.is_valid;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+			       (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#else
+	(void)allows;
+#endif
+
+	if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
+		ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+	}
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_CLR_26M_RECORD |
+				      MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				      MT_SPM_EX_OP_HW_S1_DETECT),
+				     CONSTRAINT_DRAM_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+
+	if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
+		ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+	}
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		struct wake_status *waken = NULL;
+
+		if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+			ext_op |= MT_SPM_EX_OP_TRACE_LP;
+		}
+		mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+		status.enter_cnt++;
+
+		if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+			status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+		}
+	}
+
+	return 0;
+}
+
+int spm_get_status_rc_dram(unsigned int type, void *priv)
+{
+	int ret = MT_RM_STATUS_OK;
+
+	if (type == PLAT_RC_STATUS) {
+		int res = 0;
+		struct rc_common_state *st = (struct rc_common_state *)priv;
+
+		if (st == NULL) {
+			return MT_RM_STATUS_BAD;
+		}
+
+		res = spm_rc_constraint_status_get(st->id, st->type,
+						   st->act, MT_RM_CONSTRAINT_ID_DRAM,
+						   (struct constraint_status * const)&status,
+						   (struct constraint_status * const)st->value);
+		if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+			ret = MT_RM_STATUS_STOP;
+		}
+	}
+	return ret;
+}

plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#ifdef MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT
+#define SPM_FLAG_SRAM_SLEEP_CTRL (SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+#define SPM_SRAM_SLEEP_RC_RES_RESTRICT	(0)
+#else
+#define SPM_FLAG_SRAM_SLEEP_CTRL	(0)
+#define SPM_SRAM_SLEEP_RC_RES_RESTRICT	(0)
+#endif
+
+#define SPM_RC_UPDATE_COND_ID_MASK	(0xffff)
+#define SPM_RC_UPDATE_COND_RC_ID_MASK	(0xffff)
+#define SPM_RC_UPDATE_COND_RC_ID_SHIFT	(16)
+
+#define SPM_RC_UPDATE_COND_RC_ID_GET(val) \
+	((val >> SPM_RC_UPDATE_COND_RC_ID_SHIFT) & SPM_RC_UPDATE_COND_RC_ID_MASK)
+
+#define SPM_RC_UPDATE_COND_ID_GET(val) (val & SPM_RC_UPDATE_COND_ID_MASK)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+int spm_get_status_rc_dram(unsigned int type, void *priv);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+int spm_get_status_rc_syspll(unsigned int type, void *priv);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+int spm_get_status_rc_bus26m(unsigned int type, void *priv);
+
+#endif

plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c

@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+				 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+				 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+				 MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+				    SPM_FLAG_DISABLE_VCORE_DVS | \
+				    SPM_FLAG_DISABLE_VCORE_DFS | \
+				    SPM_FLAG_SRAM_SLEEP_CTRL | \
+				    SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+				    SPM_FLAG_ENABLE_6315_CTRL | \
+				    SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+				    SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1 (0)
+
+/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
+#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ	(MT_SPM_26M)
+#else
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ	(MT_SPM_26M)
+#endif
+
+static unsigned int syspll_ext_opand2;
+static unsigned short ext_status_syspll;
+
+static struct mt_spm_cond_tables cond_syspll = {
+	.table_cg = {
+		0xFF5DD002,	/* MTCMOS1 */
+		0x0000003C,	/* MTCMOS2 */
+		0x27AF8000,	/* INFRA0  */
+		0x20010876,	/* INFRA1  */
+		0x86000640,	/* INFRA2  */
+		0x30008020,	/* INFRA3  */
+		0x80000000,	/* INFRA4  */
+		0x01002A0B,	/* PERI0   */
+		0x00090000,	/* VPPSYS0_0  */
+		0x38FF3E69,     /* VPPSYS0_1  */
+		0xF0081450,	/* VPPSYS1_0  */
+		0x00003000,     /* VPPSYS1_1  */
+		0x00000000,	/* VDOSYS0_0  */
+		0x00000000,     /* VDOSYS0_1  */
+		0x000001FF,	/* VDOSYS1_0  */
+		0x008001E0,     /* VDOSYS1_1  */
+		0x00FB0007,	/* VDOSYS1_2  */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_SYSPLL,
+	.is_valid = (MT_SPM_RC_VALID_SW |
+		     MT_SPM_RC_VALID_COND_CHECK |
+		     MT_SPM_RC_VALID_COND_LATCH |
+		     MT_SPM_RC_VALID_XSOC_BBLPM |
+		     MT_SPM_RC_VALID_TRACE_TIME),
+	.is_cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_syspll_res,
+	.residency = 0ULL,
+};
+
+int spm_syspll_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+	unsigned int res_req = CONSTRAINT_SYSPLL_RESOURCE_REQ;
+
+	if ((spm_lp == NULL) || (resource_req == NULL)) {
+		return -1;
+	}
+
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+
+	*resource_req |= res_req;
+	return 0;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+	return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
+		IS_MT_RM_RC_READY(status.is_valid) &&
+		(IS_PLAT_SUSPEND_ID(state_id) ||
+		 (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
+		 (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+	int res = MT_RM_STATUS_OK;
+
+	const struct mt_spm_cond_tables * const tlb =
+		(const struct mt_spm_cond_tables * const)val;
+	const struct mt_spm_cond_tables *tlb_check =
+		(const struct mt_spm_cond_tables *)&cond_syspll;
+
+	if (tlb == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+						 (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+						 &cond_syspll_res : NULL);
+	return res;
+}
+
+static void update_rc_clkbuf_status(const void *val)
+{
+	unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
+
+	if (is_flight != 0U) {
+		spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
+					    MT_RM_CONSTRAINT_ID_SYSPLL,
+					    MT_SPM_RC_VALID_FLIGHTMODE,
+					    (struct constraint_status * const)&status);
+	} else {
+		spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
+					    MT_RM_CONSTRAINT_ID_SYSPLL,
+					    MT_SPM_RC_VALID_FLIGHTMODE,
+					    (struct constraint_status * const)&status);
+	}
+}
+
+static void update_rc_ufs_status(const void *val)
+{
+	unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
+
+	if (is_ufs_h8 != 0U) {
+		spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
+					    MT_RM_CONSTRAINT_ID_SYSPLL,
+					    MT_SPM_RC_VALID_UFS_H8,
+					    (struct constraint_status * const)&status);
+	} else {
+		spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
+					    MT_RM_CONSTRAINT_ID_SYSPLL,
+					    MT_SPM_RC_VALID_UFS_H8,
+					    (struct constraint_status * const)&status);
+	}
+}
+
+static void update_rc_usb_peri(const void *val)
+{
+	int *flag = (int *)val;
+
+	if (flag == NULL) {
+		return;
+	}
+
+	if (*flag != 0) {
+		SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+	} else {
+		SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+	}
+}
+
+static void update_rc_usb_infra(const void *val)
+{
+	int *flag = (int *)val;
+
+	if (flag == NULL) {
+		return;
+	}
+
+	if (*flag != 0) {
+		SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+	} else {
+		SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+	}
+}
+
+static void update_rc_status(const void *val)
+{
+	const struct rc_common_state *st;
+
+	st = (const struct rc_common_state *)val;
+
+	if (st == NULL) {
+		return;
+	}
+
+	if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+		struct mt_spm_cond_tables * const tlb = &cond_syspll;
+
+		spm_rc_condition_modifier(st->id, st->act, st->value,
+					  MT_RM_CONSTRAINT_ID_SYSPLL, tlb);
+	} else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+		   (st->type == CONSTRAINT_RESIDNECY)) {
+		spm_rc_constraint_status_set(st->id, st->type, st->act,
+					     MT_RM_CONSTRAINT_ID_SYSPLL,
+					     (struct constraint_status * const)st->value,
+					     (struct constraint_status * const)&status);
+	} else {
+		INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+	}
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+	int res = MT_RM_STATUS_OK;
+
+	switch (type) {
+	case PLAT_RC_UPDATE_CONDITION:
+		res = update_rc_condition(val);
+		break;
+	case PLAT_RC_CLKBUF_STATUS:
+		update_rc_clkbuf_status(val);
+		break;
+	case PLAT_RC_UFS_STATUS:
+		update_rc_ufs_status(val);
+		break;
+	case PLAT_RC_IS_USB_PERI:
+		update_rc_usb_peri(val);
+		break;
+	case PLAT_RC_IS_USB_INFRA:
+		update_rc_usb_infra(val);
+		break;
+	case PLAT_RC_STATUS:
+		update_rc_status(val);
+		break;
+	default:
+		INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+		break;
+	}
+	return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+	return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	ext_status_syspll = status.is_valid;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+			       MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
+#else
+	(void)allows;
+#endif
+	if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
+		ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+	}
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (syspll_ext_opand2 | MT_SPM_EX_OP_CLR_26M_RECORD |
+				      MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE),
+				     CONSTRAINT_SYSPLL_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+	if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
+		ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+	}
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (syspll_ext_opand2 | MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				       MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		struct wake_status *waken = NULL;
+
+		if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+			ext_op |= MT_SPM_EX_OP_TRACE_LP;
+		}
+
+		mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+		status.enter_cnt++;
+
+		if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+			status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+		}
+	}
+
+	return 0;
+}
+
+int spm_get_status_rc_syspll(unsigned int type, void *priv)
+{
+	int ret = MT_RM_STATUS_OK;
+
+	if (type == PLAT_RC_STATUS) {
+		int res = 0;
+		struct rc_common_state *st = (struct rc_common_state *)priv;
+
+		if (st == NULL) {
+			return MT_RM_STATUS_BAD;
+		}
+
+		res = spm_rc_constraint_status_get(st->id, st->type, st->act,
+						   MT_RM_CONSTRAINT_ID_SYSPLL,
+						   (struct constraint_status * const)&status,
+						   (struct constraint_status * const)st->value);
+		if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+			ret = MT_RM_STATUS_STOP;
+		}
+	}
+	return ret;
+}

plat/mediatek/drivers/spm/mt8188/mt_spm.c

@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <arch.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include "constraints/mt_spm_rc_internal.h"
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
+#include <lpm/mt_lp_rqm.h>
+#include <lpm/mt_lpm_smc.h>
+#include "mt_spm.h"
+#include "mt_spm_cond.h"
+#include "mt_spm_conservation.h"
+#include "mt_spm_constraint.h"
+#include "mt_spm_idle.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include "mt_spm_suspend.h"
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+#include "sleep_def.h"
+
+/*
+ * System Power Manager (SPM) is a hardware module which provides CPU idle
+ * and system suspend features.
+ */
+
+spinlock_t spm_lock;
+
+#ifdef MTK_PLAT_SPM_UNSUPPORT
+struct mt_resource_manager plat_mt8188_rm = {
+};
+#else
+struct mt_lp_res_req rq_xo_fpm = {
+	.res_id = MT_LP_RQ_XO_FPM,
+	.res_rq = MT_SPM_XO_FPM,
+	.res_usage = 0,
+};
+
+struct mt_lp_res_req rq_26m = {
+	.res_id = MT_LP_RQ_26M,
+	.res_rq = MT_SPM_26M,
+	.res_usage = 0,
+};
+
+struct mt_lp_res_req rq_infra = {
+	.res_id = MT_LP_RQ_INFRA,
+	.res_rq = MT_SPM_INFRA,
+	.res_usage = 0,
+};
+
+struct mt_lp_res_req rq_syspll = {
+	.res_id = MT_LP_RQ_SYSPLL,
+	.res_rq = MT_SPM_SYSPLL,
+	.res_usage = 0,
+};
+
+struct mt_lp_res_req rq_dram_s0 = {
+	.res_id = MT_LP_RQ_DRAM,
+	.res_rq = MT_SPM_DRAM_S0,
+	.res_usage = 0,
+};
+
+struct mt_lp_res_req rq_dram_s1 = {
+	.res_id = MT_LP_RQ_DRAM,
+	.res_rq = MT_SPM_DRAM_S1,
+	.res_usage = 0,
+};
+
+struct mt_lp_res_req *spm_resources[] = {
+	&rq_xo_fpm,
+	&rq_26m,
+	&rq_infra,
+	&rq_syspll,
+	&rq_dram_s0,
+	&rq_dram_s1,
+	NULL,
+};
+
+struct mt_resource_req_manager plat_mt8188_rq = {
+	.res = spm_resources,
+};
+
+struct mt_resource_constraint plat_constraint_bus26m = {
+	.is_valid = spm_is_valid_rc_bus26m,
+	.update = spm_update_rc_bus26m,
+	.allow = spm_allow_rc_bus26m,
+	.run = spm_run_rc_bus26m,
+	.reset = spm_reset_rc_bus26m,
+	.get_status = spm_get_status_rc_bus26m,
+};
+
+struct mt_resource_constraint plat_constraint_syspll = {
+	.is_valid = spm_is_valid_rc_syspll,
+	.update = spm_update_rc_syspll,
+	.allow = spm_allow_rc_syspll,
+	.run = spm_run_rc_syspll,
+	.reset = spm_reset_rc_syspll,
+	.get_status = spm_get_status_rc_syspll,
+};
+
+struct mt_resource_constraint plat_constraint_dram = {
+	.is_valid = spm_is_valid_rc_dram,
+	.update = spm_update_rc_dram,
+	.allow = spm_allow_rc_dram,
+	.run = spm_run_rc_dram,
+	.reset = spm_reset_rc_dram,
+	.get_status = spm_get_status_rc_dram,
+};
+
+struct mt_resource_constraint plat_constraint_cpu = {
+	.is_valid = spm_is_valid_rc_cpu_buck_ldo,
+	.update = spm_update_rc_cpu_buck_ldo,
+	.allow = spm_allow_rc_cpu_buck_ldo,
+	.run = spm_run_rc_cpu_buck_ldo,
+	.reset = spm_reset_rc_cpu_buck_ldo,
+	.get_status = spm_get_status_rc_cpu_buck_ldo,
+};
+
+struct mt_resource_constraint *plat_constraints[] = {
+	&plat_constraint_bus26m,
+	&plat_constraint_syspll,
+	&plat_constraint_dram,
+	&plat_constraint_cpu,
+	NULL,
+};
+
+struct mt_resource_manager plat_mt8188_rm = {
+	.update = mt_spm_cond_update,
+	.consts = plat_constraints,
+};
+#endif
+
+/* Determine for SPM software resource user */
+static struct mt_lp_resource_user spm_res_user;
+
+struct mt_lp_resource_user *get_spm_res_user(void)
+{
+	return &spm_res_user;
+}
+
+int spm_boot_init(void)
+{
+	mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+	mt_lp_rm_register(&plat_mt8188_rm);
+
+	/* SPM service won't run when SPM not ready */
+#ifndef MTK_PLAT_SPM_UNSUPPORT
+	mt_lp_resource_request_manager_register(&plat_mt8188_rq);
+	mt_lp_resource_user_register("SPM", &spm_res_user);
+#endif
+
+	return 0;
+}
+MTK_ARCH_INIT(spm_boot_init);

plat/mediatek/drivers/spm/mt8188/mt_spm.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_H
+#define MT_SPM_H
+
+#include <stdint.h>
+#include <stdio.h>
+#include <lib/spinlock.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rq.h>
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. Therefore, there is no doubt to use the spin_lock here.
+ */
+extern spinlock_t spm_lock;
+
+#ifdef __GNUC__
+#define spm_likely(x)	__builtin_expect(!!(x), 1)
+#define spm_unlikely(x)	__builtin_expect(!!(x), 0)
+#else
+#define spm_likely(x)	(x)
+#define spm_unlikely(x)	(x)
+#endif
+
+#define MT_SPM_USING_SRCLKEN_RC
+/* spm extern operand definition */
+#define MT_SPM_EX_OP_CLR_26M_RECORD		BIT(0)
+#define MT_SPM_EX_OP_SET_WDT			BIT(1)
+#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ	BIT(2)
+#define MT_SPM_EX_OP_SET_SUSPEND_MODE		BIT(3)
+#define MT_SPM_EX_OP_SET_IS_ADSP		BIT(4)
+#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM		BIT(5)
+#define MT_SPM_EX_OP_HW_S1_DETECT		BIT(6)
+#define MT_SPM_EX_OP_TRACE_LP			BIT(7)
+#define MT_SPM_EX_OP_TRACE_SUSPEND		BIT(8)
+#define MT_SPM_EX_OP_TRACE_TIMESTAMP_EN		BIT(9)
+#define MT_SPM_EX_OP_TIME_CHECK			BIT(10)
+#define MT_SPM_EX_OP_TIME_OBS			BIT(11)
+#define MT_SPM_EX_OP_PERI_ON			BIT(12)
+#define MT_SPM_EX_OP_INFRA_ON			BIT(13)
+
+typedef enum {
+	WR_NONE = 0,
+	WR_UART_BUSY = 1,
+	WR_ABORT = 2,
+	WR_PCM_TIMER = 3,
+	WR_WAKE_SRC = 4,
+	WR_DVFSRC = 5,
+	WR_TWAM = 6,
+	WR_PMSR = 7,
+	WR_SPM_ACK_CHK = 8,
+	WR_UNKNOWN = 9,
+} wake_reason_t;
+
+struct mt_lp_resource_user *get_spm_res_user(void);
+int spm_boot_init(void);
+
+#endif /* MT_SPM_H */

plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c

@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <lib/mmio.h>
+#include <lib/pm/mtk_pm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <platform_def.h>
+
+#define TOPCKGEB_BASE			(IO_PHYS)
+
+#define MT_LP_TZ_INFRA_REG(ofs)		(INFRACFG_AO_BASE + ofs)
+
+#define MT_LP_TZ_SPM_REG(ofs)		(SPM_BASE + ofs)
+#define MT_LP_TZ_TOPCK_REG(ofs)		(TOPCKGEB_BASE + ofs)
+#define MT_LP_TZ_APMIXEDSYS(ofs)	(APMIXEDSYS + ofs)
+
+#define MT_LP_TZ_VPPSYS0_REG(ofs)	(VPPSYS0_BASE + ofs)
+#define MT_LP_TZ_VPPSYS1_REG(ofs)	(VPPSYS1_BASE + ofs)
+#define MT_LP_TZ_VDOSYS0_REG(ofs)	(VDOSYS0_BASE + ofs)
+#define MT_LP_TZ_VDOSYS1_REG(ofs)	(VDOSYS1_BASE + ofs)
+
+#define MT_LP_TZ_PERI_AO_REG(ofs)	(PERICFG_AO_BASE + ofs)
+
+#undef SPM_PWR_STATUS
+#define SPM_PWR_STATUS			MT_LP_TZ_SPM_REG(0x016C)
+#define SPM_PWR_STATUS_2ND		MT_LP_TZ_SPM_REG(0x0170)
+#define SPM_CPU_PWR_STATUS		MT_LP_TZ_SPM_REG(0x0174)
+#define	INFRA_SW_CG0			MT_LP_TZ_INFRA_REG(0x0090)
+#define	INFRA_SW_CG1			MT_LP_TZ_INFRA_REG(0x0094)
+#define	INFRA_SW_CG2			MT_LP_TZ_INFRA_REG(0x00AC)
+#define	INFRA_SW_CG3			MT_LP_TZ_INFRA_REG(0x00C8)
+#define	INFRA_SW_CG4			MT_LP_TZ_INFRA_REG(0x00E8)
+#define	TOP_SW_I2C_CG			MT_LP_TZ_TOPCK_REG(0x00A4)
+#define	PERI_SW_CG0			MT_LP_TZ_PERI_AO_REG(0x0018)
+#define	VPPSYS0_SW_CG0			MT_LP_TZ_VPPSYS0_REG(0x0020)
+#define	VPPSYS0_SW_CG1			MT_LP_TZ_VPPSYS0_REG(0x002C)
+#define	VPPSYS0_SW_CG2			MT_LP_TZ_VPPSYS0_REG(0x0038)
+#define	VPPSYS1_SW_CG0			MT_LP_TZ_VPPSYS1_REG(0x0100)
+#define	VPPSYS1_SW_CG1			MT_LP_TZ_VPPSYS1_REG(0x0110)
+#define	VDOSYS0_SW_CG0			MT_LP_TZ_VDOSYS0_REG(0x0100)
+#define	VDOSYS0_SW_CG1			MT_LP_TZ_VDOSYS0_REG(0x0110)
+#define	VDOSYS1_SW_CG0			MT_LP_TZ_VDOSYS1_REG(0x0100)
+#define	VDOSYS1_SW_CG1			MT_LP_TZ_VDOSYS1_REG(0x0120)
+#define	VDOSYS1_SW_CG2			MT_LP_TZ_VDOSYS1_REG(0x0130)
+
+#define CLK_CFG(id)			MT_LP_TZ_TOPCK_REG(0x2c + id * 0xc)
+
+enum {
+	/* CLK_CFG_0 1000_002c */
+	CLKMUX_VPP	= 0,
+	NF_CLKMUX,
+};
+
+#define CLK_CHECK BIT(31)
+
+static bool check_clkmux_pdn(unsigned int clkmux_id)
+{
+	unsigned int reg, val, idx;
+	bool ret = false;
+
+	if ((clkmux_id & CLK_CHECK) != 0U) {
+		clkmux_id = (clkmux_id & ~CLK_CHECK);
+		reg = clkmux_id / 4U;
+		val = mmio_read_32(CLK_CFG(reg));
+		idx = clkmux_id % 4U;
+		ret = (((val >> (idx * 8U)) & 0x80) != 0U);
+	}
+
+	return ret;
+}
+
+static struct mt_spm_cond_tables spm_cond_t;
+
+/* local definitions */
+struct idle_cond_info {
+	/* check SPM_PWR_STATUS for bit definition */
+	unsigned int subsys_mask;
+	/* cg address */
+	uintptr_t addr;
+	/* bitflip value from *addr ? */
+	bool bBitflip;
+	/* check clkmux if bit 31 = 1, id is bit[30:0] */
+	unsigned int clkmux_id;
+};
+
+#define IDLE_CG(mask, addr, bitflip, clkmux)	{mask, (uintptr_t)addr, bitflip, clkmux}
+
+static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
+	IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0),
+	IDLE_CG(0xffffffff, SPM_CPU_PWR_STATUS, false, 0),
+	IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0),
+	IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0),
+	IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0),
+	IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0),
+	IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0),
+	IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0),
+	IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+	IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+	IDLE_CG(0x00001000, VPPSYS1_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+	IDLE_CG(0x00001000, VPPSYS1_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+	IDLE_CG(0x00002000, VDOSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+	IDLE_CG(0x00002000, VDOSYS0_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+	IDLE_CG(0x00004000, VDOSYS1_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+	IDLE_CG(0x00004000, VDOSYS1_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+	IDLE_CG(0x00004000, VDOSYS1_SW_CG2, true, (CLK_CHECK | CLKMUX_VPP)),
+};
+
+/* check pll idle condition */
+#define PLL_MFGPLL	MT_LP_TZ_APMIXEDSYS(0x340)
+#define PLL_MMPLL	MT_LP_TZ_APMIXEDSYS(0x544)
+#define PLL_UNIVPLL	MT_LP_TZ_APMIXEDSYS(0x504)
+#define PLL_MSDCPLL	MT_LP_TZ_APMIXEDSYS(0x514)
+#define PLL_TVDPLL1	MT_LP_TZ_APMIXEDSYS(0x524)
+#define PLL_TVDPLL2	MT_LP_TZ_APMIXEDSYS(0x534)
+#define PLL_ETHPLL	MT_LP_TZ_APMIXEDSYS(0x44c)
+#define PLL_IMGPLL	MT_LP_TZ_APMIXEDSYS(0x554)
+#define PLL_APLL1	MT_LP_TZ_APMIXEDSYS(0x304)
+#define PLL_APLL2	MT_LP_TZ_APMIXEDSYS(0x318)
+#define PLL_APLL3	MT_LP_TZ_APMIXEDSYS(0x32c)
+#define PLL_APLL4	MT_LP_TZ_APMIXEDSYS(0x404)
+#define PLL_APLL5	MT_LP_TZ_APMIXEDSYS(0x418)
+
+unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+			       const struct mt_spm_cond_tables *dest,
+			       struct mt_spm_cond_tables *res)
+{
+	unsigned int b_res = 0U;
+	unsigned int i;
+
+	if ((src == NULL) || (dest == NULL)) {
+		return SPM_COND_CHECK_FAIL;
+	}
+
+	for (i = 0; i < PLAT_SPM_COND_MAX; i++) {
+		if (res != NULL) {
+			res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]);
+
+			if ((res->table_cg[i]) != 0U) {
+				b_res |= BIT(i);
+			}
+		} else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
+			b_res |= BIT(i);
+			break;
+		}
+	}
+
+	if (res != NULL) {
+		res->table_pll = (src->table_pll & dest->table_pll);
+
+		if ((res->table_pll) != 0U) {
+			b_res |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
+				 SPM_COND_CHECK_BLOCKED_PLL;
+		}
+	} else if ((src->table_pll & dest->table_pll) != 0U) {
+		b_res |= SPM_COND_CHECK_BLOCKED_PLL;
+	}
+
+	return b_res;
+}
+
+unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
+				 const struct mt_spm_cond_tables *dest,
+				 struct mt_spm_cond_tables *res)
+{
+	unsigned int b_res = 0U;
+
+	if (res != NULL) {
+		res->table_all_pll = src->table_all_pll;
+		if ((res->table_all_pll) != 0U) {
+			b_res |= (res->table_all_pll << SPM_COND_BLOCKED_PLL_IDX) |
+				 SPM_COND_CHECK_BLOCKED_PLL;
+		}
+	} else if ((src->table_pll & dest->table_pll) != 0U) {
+		b_res |= SPM_COND_CHECK_BLOCKED_PLL;
+	}
+
+	return b_res;
+}
+
+#define IS_MT_SPM_PWR_OFF(mask) \
+	(!(mmio_read_32(SPM_PWR_STATUS) & mask) && \
+	 !(mmio_read_32(SPM_PWR_STATUS_2ND) & mask))
+
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+		       int stateid, void *priv)
+{
+	static const struct {
+		uintptr_t en_reg;
+		uint32_t pll_b;
+	} plls[] = {
+		{ PLL_MFGPLL, PLL_BIT_MFGPLL },
+		{ PLL_MMPLL, PLL_BIT_MMPLL },
+		{ PLL_UNIVPLL, PLL_BIT_UNIVPLL },
+		{ PLL_MSDCPLL, PLL_BIT_MSDCPLL },
+		{ PLL_TVDPLL1, PLL_BIT_TVDPLL1 },
+		{ PLL_TVDPLL2, PLL_BIT_TVDPLL2 },
+		{ PLL_ETHPLL, PLL_BIT_ETHPLL },
+		{ PLL_IMGPLL, PLL_BIT_IMGPLL },
+		{ PLL_APLL1, PLL_BIT_APLL1 },
+		{ PLL_APLL2, PLL_BIT_APLL2 },
+		{ PLL_APLL3, PLL_BIT_APLL3 },
+		{ PLL_APLL4, PLL_BIT_APLL4 },
+		{ PLL_APLL5, PLL_BIT_APLL5 },
+	};
+
+	int res;
+	unsigned int i;
+	struct mt_resource_constraint *const *_con;
+
+	/* read all cg state */
+	for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+		spm_cond_t.table_cg[i] = 0U;
+
+		/* check mtcmos, if off set idle_value and clk to 0 disable */
+		if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
+			continue;
+		}
+		/* check clkmux */
+		if (check_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
+			continue;
+		}
+		spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
+					 ~mmio_read_32(idle_cg_info[i].addr) :
+					 mmio_read_32(idle_cg_info[i].addr);
+	}
+
+	spm_cond_t.table_pll = 0U;
+	for (i = 0U; i < ARRAY_SIZE(plls); i++) {
+		if ((mmio_read_32(plls[i].en_reg) & BIT(9)) != 0U) {
+			spm_cond_t.table_pll |= plls[i].pll_b;
+		}
+	}
+
+	spm_cond_t.priv = priv;
+	for (i = 0U, _con = con; (*_con != NULL) && (i < num); _con++, i++) {
+		if ((*_con)->update == NULL) {
+			continue;
+		}
+		res = (*_con)->update(stateid, PLAT_RC_UPDATE_CONDITION,
+				      (void const *)&spm_cond_t);
+		if (res != MT_RM_STATUS_OK) {
+			break;
+		}
+	}
+
+	return 0;
+}

plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_COND_H
+#define MT_SPM_COND_H
+
+#include <lpm/mt_lp_rm.h>
+
+enum plat_spm_cond {
+	PLAT_SPM_COND_MTCMOS1 = 0,
+	PLAT_SPM_COND_MTCMOS2,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_INFRA_4,
+	PLAT_SPM_COND_CG_PERI_0,
+	PLAT_SPM_COND_CG_VPPSYS0_0,
+	PLAT_SPM_COND_CG_VPPSYS0_1,
+	PLAT_SPM_COND_CG_VPPSYS1_0,
+	PLAT_SPM_COND_CG_VPPSYS1_1,
+	PLAT_SPM_COND_CG_VDOSYS0_0,
+	PLAT_SPM_COND_CG_VDOSYS0_1,
+	PLAT_SPM_COND_CG_VDOSYS1_0,
+	PLAT_SPM_COND_CG_VDOSYS1_1,
+	PLAT_SPM_COND_CG_VDOSYS1_2,
+	PLAT_SPM_COND_MAX,
+};
+
+/* For PLL id >= PLAT_SPM_COND_PLL_MAX is not checked in idle condition  */
+enum plat_spm_cond_pll {
+	PLAT_SPM_COND_PLL_UNIVPLL = 0,
+	PLAT_SPM_COND_PLL_MFGPLL,
+	PLAT_SPM_COND_PLL_MSDCPLL,
+	PLAT_SPM_COND_PLL_TVDPLL1,
+	PLAT_SPM_COND_PLL_TVDPLL2,
+	PLAT_SPM_COND_PLL_MMPLL,
+	PLAT_SPM_COND_PLL_ETHPLL,
+	PLAT_SPM_COND_PLL_IMGPLL,
+	PLAT_SPM_COND_PLL_APLL1,
+	PLAT_SPM_COND_PLL_APLL2,
+	PLAT_SPM_COND_PLL_APLL3,
+	PLAT_SPM_COND_PLL_APLL4,
+	PLAT_SPM_COND_PLL_APLL5,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#define PLL_BIT_MFGPLL	BIT(PLAT_SPM_COND_PLL_MFGPLL)
+#define PLL_BIT_MMPLL	BIT(PLAT_SPM_COND_PLL_MMPLL)
+#define PLL_BIT_UNIVPLL	BIT(PLAT_SPM_COND_PLL_UNIVPLL)
+#define PLL_BIT_MSDCPLL	BIT(PLAT_SPM_COND_PLL_MSDCPLL)
+#define PLL_BIT_TVDPLL1	BIT(PLAT_SPM_COND_PLL_TVDPLL1)
+#define PLL_BIT_TVDPLL2	BIT(PLAT_SPM_COND_PLL_TVDPLL2)
+#define PLL_BIT_ETHPLL	BIT(PLAT_SPM_COND_PLL_ETHPLL)
+#define PLL_BIT_IMGPLL	BIT(PLAT_SPM_COND_PLL_IMGPLL)
+#define PLL_BIT_APLL1	BIT(PLAT_SPM_COND_PLL_APLL1)
+#define PLL_BIT_APLL2	BIT(PLAT_SPM_COND_PLL_APLL2)
+#define PLL_BIT_APLL3   BIT(PLAT_SPM_COND_PLL_APLL3)
+#define PLL_BIT_APLL4	BIT(PLAT_SPM_COND_PLL_APLL4)
+#define PLL_BIT_APLL5	BIT(PLAT_SPM_COND_PLL_APLL5)
+
+/*
+ * Definition about SPM_COND_CHECK_BLOCKED
+ * bit[00:16]: cg blocking index
+ * bit[17:29]: pll blocking index
+ * bit[30]: pll blocking information
+ * bit[31]: idle condition check fail
+ */
+#define SPM_COND_BLOCKED_CG_IDX		(0)
+#define SPM_COND_BLOCKED_PLL_IDX	(17)
+#define SPM_COND_CHECK_BLOCKED_PLL	BIT(30)
+#define SPM_COND_CHECK_FAIL		BIT(31)
+
+struct mt_spm_cond_tables {
+	unsigned int table_cg[PLAT_SPM_COND_MAX];
+	unsigned int table_pll;
+	unsigned int table_all_pll;
+	void *priv;
+};
+
+unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+			       const struct mt_spm_cond_tables *dest,
+			       struct mt_spm_cond_tables *res);
+unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
+				 const struct mt_spm_cond_tables *dest,
+				 struct mt_spm_cond_tables *res);
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+		       int stateid, void *priv);
+
+#endif

plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rqm.h>
+#include "mt_spm.h"
+#include "mt_spm_conservation.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+#define INFRA_EMI_DCM_CFG0	U(0x10002028)
+
+static struct wake_status spm_wakesta; /* record last wakesta */
+static wake_reason_t spm_wake_reason = WR_NONE;
+static unsigned int emi_bak;
+
+static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
+				struct spm_lp_scen *spm_lp,
+				unsigned int resource_req)
+{
+	int ret = 0;
+	struct pwr_ctrl *pwrctrl;
+	unsigned int cpu = plat_my_core_pos();
+
+	pwrctrl = spm_lp->pwrctrl;
+
+	/* EMI workaround */
+	emi_bak = mmio_read_32(INFRA_EMI_DCM_CFG0) & BIT(22);
+	mmio_setbits_32(INFRA_EMI_DCM_CFG0, BIT(22));
+
+	__spm_set_cpu_status(cpu);
+	__spm_set_power_control(pwrctrl);
+	__spm_set_wakeup_event(pwrctrl);
+
+	__spm_set_pcm_flags(pwrctrl);
+
+	__spm_src_req_update(pwrctrl, resource_req);
+
+	if ((ext_opand & MT_SPM_EX_OP_CLR_26M_RECORD) != 0U) {
+		__spm_clean_before_wfi();
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+		__spm_set_pcm_wdt(1);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+		spm_hw_s1_state_monitor_resume();
+	}
+
+	__spm_send_cpu_wakeup_event();
+
+	return ret;
+}
+
+static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
+				struct spm_lp_scen *spm_lp,
+				struct wake_status **status)
+{
+	unsigned int ext_status = 0U;
+
+	if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+		__spm_set_pcm_wdt(0);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+		spm_hw_s1_state_monitor_pause(&ext_status);
+	}
+
+	__spm_ext_int_wakeup_req_clr();
+
+	__spm_get_wakeup_status(&spm_wakesta, ext_status);
+
+	if (status != NULL) {
+		*status = &spm_wakesta;
+	}
+
+	__spm_clean_after_wakeup();
+	spm_wake_reason = __spm_output_wake_reason(&spm_wakesta);
+
+	/* EMI workaround */
+	if (emi_bak == 0U) {
+		mmio_clrbits_32(INFRA_EMI_DCM_CFG0, BIT(22));
+	}
+}
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+		     struct spm_lp_scen *spm_lp,
+		     unsigned int resource_req)
+{
+	unsigned int rc_state = resource_req;
+
+	if (spm_lp == NULL) {
+		return -1;
+	}
+
+	spin_lock(&spm_lock);
+	go_to_spm_before_wfi(state_id, ext_opand, spm_lp, rc_state);
+	spin_unlock(&spm_lock);
+
+	return 0;
+}
+
+void spm_conservation_finish(int state_id, unsigned int ext_opand, struct spm_lp_scen *spm_lp,
+			     struct wake_status **status)
+{
+	spin_lock(&spm_lock);
+	go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
+	spin_unlock(&spm_lock);
+}
+
+int spm_conservation_get_result(struct wake_status **res)
+{
+	if (res == NULL) {
+		return -1;
+	}
+	*res = &spm_wakesta;
+	return 0;
+}

plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSERVATION_H
+#define MT_SPM_CONSERVATION_H
+
+#include "mt_spm_internal.h"
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+		     struct spm_lp_scen *spm_lp,
+		     unsigned int resource_req);
+void spm_conservation_finish(int state_id, unsigned int ext_opand,
+			     struct spm_lp_scen *spm_lp,
+			     struct wake_status **status);
+int spm_conservation_get_result(struct wake_status **res);
+
+#endif /* MT_SPM_CONSERVATION_H */

plat/mediatek/drivers/spm/mt8188/mt_spm_constraint.h

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <lpm/mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF	BIT(0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0		BIT(1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1		BIT(2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP		BIT(3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN	BIT(4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF	BIT(5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND	BIT(6)
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM		BIT(7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS		BIT(8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE	BIT(9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE	BIT(10)
+
+enum mt_spm_rm_rc_type {
+	MT_RM_CONSTRAINT_ID_BUS26M,
+	MT_RM_CONSTRAINT_ID_SYSPLL,
+	MT_RM_CONSTRAINT_ID_DRAM,
+	MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
+	MT_RM_CONSTRAINT_ID_ALL,
+};
+
+#define MT_SPM_RC_INVALID		(0x0)
+#define MT_SPM_RC_VALID_SW		BIT(0)
+#define MT_SPM_RC_VALID_FW		BIT(1)
+#define MT_SPM_RC_VALID_RESIDNECY	BIT(2)
+#define MT_SPM_RC_VALID_COND_CHECK	BIT(3)
+#define MT_SPM_RC_VALID_COND_LATCH	BIT(4)
+#define MT_SPM_RC_VALID_UFS_H8		BIT(5)
+#define MT_SPM_RC_VALID_FLIGHTMODE	BIT(6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM	BIT(7)
+#define MT_SPM_RC_VALID_TRACE_EVENT	BIT(8)
+#define MT_SPM_RC_VALID_TRACE_TIME	BIT(9)
+
+/* MT_RM_CONSTRAINT_SW_VALID | MT_RM_CONSTRAINT_FW_VALID */
+#define MT_SPM_RC_VALID	(MT_SPM_RC_VALID_SW)
+
+#define IS_MT_RM_RC_READY(status)	((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+struct constraint_status {
+	uint16_t id;
+	uint16_t is_valid;
+	uint32_t is_cond_block;
+	uint32_t enter_cnt;
+	uint32_t all_pll_dump;
+	uint64_t residency;
+	struct mt_spm_cond_tables *cond_res;
+};
+
+enum constraint_status_update_type {
+	CONSTRAINT_UPDATE_VALID,
+	CONSTRAINT_UPDATE_COND_CHECK,
+	CONSTRAINT_RESIDNECY,
+};
+
+enum constraint_status_get_type {
+	CONSTRAINT_GET_VALID = 0xD0000000,
+	CONSTRAINT_GET_ENTER_CNT,
+	CONSTRAINT_GET_RESIDENCY,
+	CONSTRAINT_GET_COND_EN,
+	CONSTRAINT_COND_BLOCK,
+	CONSTRAINT_GET_COND_BLOCK_LATCH,
+	CONSTRAINT_GET_COND_BLOCK_DETAIL,
+	CONSTRAINT_GET_RESIDNECY,
+};
+
+struct rc_common_state {
+	unsigned int id;
+	unsigned int act;
+	unsigned int type;
+	void *value;
+};
+
+#define MT_SPM_RC_BBLPM_MODE	(MT_SPM_RC_VALID_UFS_H8 | \
+				 MT_SPM_RC_VALID_FLIGHTMODE | \
+				 MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st) ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+#endif /* MT_SPM_CONSTRAINT_H */

plat/mediatek/drivers/spm/mt8188/mt_spm_idle.c

@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+
+#define SPM_BYPASS_SYSPWREQ_GENERIC (1)
+
+#define __WAKE_SRC_FOR_IDLE_COMMON__ ( \
+		(R12_PCM_TIMER) | \
+		(R12_KP_IRQ_B) | \
+		(R12_APWDT_EVENT_B) | \
+		(R12_APXGPT1_EVENT_B) | \
+		(R12_MSDC_WAKEUP_B) | \
+		(R12_EINT_EVENT_B) | \
+		(R12_SBD_INTR_WAKEUP_B) | \
+		(R12_SSPM2SPM_WAKEUP_B) | \
+		(R12_SCP2SPM_WAKEUP_B) | \
+		(R12_ADSP2SPM_WAKEUP_B) | \
+		(R12_USBX_CDSC_B) | \
+		(R12_USBX_POWERDWN_B) | \
+		(R12_SYS_TIMER_EVENT_B) | \
+		(R12_EINT_EVENT_SECURE_B) | \
+		(R12_ECE_INT_HDMI_B) | \
+		(R12_AFE_IRQ_MCU_B) | \
+		(R12_SYS_CIRQ_IRQ_B) | \
+		(R12_PCIE_WAKEUPEVENT_B) | \
+		(R12_SPM_CPU_WAKEUPEVENT_B) | \
+		(R12_APUSYS_WAKE_HOST_B))
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_IDLE	(__WAKE_SRC_FOR_IDLE_COMMON__)
+#else
+#define WAKE_SRC_FOR_IDLE	(__WAKE_SRC_FOR_IDLE_COMMON__ | R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl idle_spm_pwr = {
+	.wake_src = WAKE_SRC_FOR_IDLE,
+
+	/* SPM_AP_STANDBY_CON */
+	/* [0] */
+	.reg_wfi_op = 0,
+	/* [1] */
+	.reg_wfi_type = 0,
+	/* [2] */
+	.reg_mp0_cputop_idle_mask = 0,
+	/* [3] */
+	.reg_mp1_cputop_idle_mask = 0,
+	/* [4] */
+	.reg_mcusys_idle_mask = 0,
+	/* [25] */
+	.reg_md_apsrc_1_sel = 0,
+	/* [26] */
+	.reg_md_apsrc_0_sel = 0,
+	/* [29] */
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC_REQ */
+	/* [0] */
+	.reg_spm_apsrc_req = 0,
+	/* [1] */
+	.reg_spm_f26m_req = 0,
+	/* [3] */
+	.reg_spm_infra_req = 0,
+	/* [4] */
+	.reg_spm_vrf18_req = 0,
+	/* [7] */
+	.reg_spm_ddr_en_req = 0,
+	/* [8] */
+	.reg_spm_dvfs_req = 0,
+	/* [9] */
+	.reg_spm_sw_mailbox_req = 0,
+	/* [10] */
+	.reg_spm_sspm_mailbox_req = 0,
+	/* [11] */
+	.reg_spm_adsp_mailbox_req = 0,
+	/* [12] */
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	/* [0] */
+	.reg_sspm_srcclkena_0_mask_b = 1,
+	/* [1] */
+	.reg_sspm_infra_req_0_mask_b = 1,
+	/* [2] */
+	.reg_sspm_apsrc_req_0_mask_b = 1,
+	/* [3] */
+	.reg_sspm_vrf18_req_0_mask_b = 1,
+	/* [4] */
+	.reg_sspm_ddr_en_0_mask_b = 1,
+	/* [5] */
+	.reg_scp_srcclkena_mask_b = 1,
+	/* [6] */
+	.reg_scp_infra_req_mask_b = 1,
+	/* [7] */
+	.reg_scp_apsrc_req_mask_b = 1,
+	/* [8] */
+	.reg_scp_vrf18_req_mask_b = 1,
+	/* [9] */
+	.reg_scp_ddr_en_mask_b = 1,
+	/* [10] */
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	/* [11] */
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	/* [12] */
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	/* [13] */
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	/* [14] */
+	.reg_audio_dsp_ddr_en_mask_b = 1,
+	/* [15] */
+	.reg_apu_srcclkena_mask_b = 1,
+	/* [16] */
+	.reg_apu_infra_req_mask_b = 1,
+	/* [17] */
+	.reg_apu_apsrc_req_mask_b = 1,
+	/* [18] */
+	.reg_apu_vrf18_req_mask_b = 1,
+	/* [19] */
+	.reg_apu_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_cpueb_srcclkena_mask_b = 1,
+	/* [21] */
+	.reg_cpueb_infra_req_mask_b = 1,
+	/* [22] */
+	.reg_cpueb_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_cpueb_vrf18_req_mask_b = 1,
+	/* [24] */
+	.reg_cpueb_ddr_en_mask_b = 1,
+	/* [25] */
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	/* [26] */
+	.reg_bak_psri_infra_req_mask_b = 0,
+	/* [27] */
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	/* [28] */
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	/* [29] */
+	.reg_bak_psri_ddr_en_mask_b = 0,
+	/* [30] */
+	.reg_cam_ddren_req_mask_b = 1,
+	/* [31] */
+	.reg_img_ddren_req_mask_b = 1,
+
+	/* SPM_SRC2_MASK */
+	/* [0] */
+	.reg_msdc0_srcclkena_mask_b = 1,
+	/* [1] */
+	.reg_msdc0_infra_req_mask_b = 1,
+	/* [2] */
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	/* [3] */
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	/* [4] */
+	.reg_msdc0_ddr_en_mask_b = 1,
+	/* [5] */
+	.reg_msdc1_srcclkena_mask_b = 1,
+	/* [6] */
+	.reg_msdc1_infra_req_mask_b = 1,
+	/* [7] */
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	/* [8] */
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	/* [9] */
+	.reg_msdc1_ddr_en_mask_b = 1,
+	/* [10] */
+	.reg_msdc2_srcclkena_mask_b = 1,
+	/* [11] */
+	.reg_msdc2_infra_req_mask_b = 1,
+	/* [12] */
+	.reg_msdc2_apsrc_req_mask_b = 1,
+	/* [13] */
+	.reg_msdc2_vrf18_req_mask_b = 1,
+	/* [14] */
+	.reg_msdc2_ddr_en_mask_b = 1,
+	/* [15] */
+	.reg_ufs_srcclkena_mask_b = 1,
+	/* [16] */
+	.reg_ufs_infra_req_mask_b = 1,
+	/* [17] */
+	.reg_ufs_apsrc_req_mask_b = 1,
+	/* [18] */
+	.reg_ufs_vrf18_req_mask_b = 1,
+	/* [19] */
+	.reg_ufs_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_usb_srcclkena_mask_b = 1,
+	/* [21] */
+	.reg_usb_infra_req_mask_b = 1,
+	/* [22] */
+	.reg_usb_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_usb_vrf18_req_mask_b = 1,
+	/* [24] */
+	.reg_usb_ddr_en_mask_b = 1,
+	/* [25] */
+	.reg_pextp_p0_srcclkena_mask_b = 1,
+	/* [26] */
+	.reg_pextp_p0_infra_req_mask_b = 1,
+	/* [27] */
+	.reg_pextp_p0_apsrc_req_mask_b = 1,
+	/* [28] */
+	.reg_pextp_p0_vrf18_req_mask_b = 1,
+	/* [29] */
+	.reg_pextp_p0_ddr_en_mask_b = 1,
+
+	/* SPM_SRC3_MASK */
+	/* [0] */
+	.reg_pextp_p1_srcclkena_mask_b = 1,
+	/* [1] */
+	.reg_pextp_p1_infra_req_mask_b = 1,
+	/* [2] */
+	.reg_pextp_p1_apsrc_req_mask_b = 1,
+	/* [3] */
+	.reg_pextp_p1_vrf18_req_mask_b = 1,
+	/* [4] */
+	.reg_pextp_p1_ddr_en_mask_b = 1,
+	/* [5] */
+	.reg_gce0_infra_req_mask_b = 1,
+	/* [6] */
+	.reg_gce0_apsrc_req_mask_b = 1,
+	/* [7] */
+	.reg_gce0_vrf18_req_mask_b = 1,
+	/* [8] */
+	.reg_gce0_ddr_en_mask_b = 1,
+	/* [9] */
+	.reg_gce1_infra_req_mask_b = 1,
+	/* [10] */
+	.reg_gce1_apsrc_req_mask_b = 1,
+	/* [11] */
+	.reg_gce1_vrf18_req_mask_b = 1,
+	/* [12] */
+	.reg_gce1_ddr_en_mask_b = 1,
+	/* [13] */
+	.reg_spm_srcclkena_reserved_mask_b = 1,
+	/* [14] */
+	.reg_spm_infra_req_reserved_mask_b = 1,
+	/* [15] */
+	.reg_spm_apsrc_req_reserved_mask_b = 1,
+	/* [16] */
+	.reg_spm_vrf18_req_reserved_mask_b = 1,
+	/* [17] */
+	.reg_spm_ddr_en_reserved_mask_b = 1,
+	/* [18] */
+	.reg_disp0_apsrc_req_mask_b = 1,
+	/* [19] */
+	.reg_disp0_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_disp1_apsrc_req_mask_b = 1,
+	/* [21] */
+	.reg_disp1_ddr_en_mask_b = 1,
+	/* [22] */
+	.reg_disp2_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_disp2_ddr_en_mask_b = 1,
+	/* [24] */
+	.reg_disp3_apsrc_req_mask_b = 1,
+	/* [25] */
+	.reg_disp3_ddr_en_mask_b = 1,
+	/* [26] */
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	/* [27] */
+	.reg_infrasys_ddr_en_mask_b = 1,
+
+	/* [28] */
+	.reg_cg_check_srcclkena_mask_b = 1,
+	/* [29] */
+	.reg_cg_check_apsrc_req_mask_b = 1,
+	/* [30] */
+	.reg_cg_check_vrf18_req_mask_b = 1,
+	/* [31] */
+	.reg_cg_check_ddr_en_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	/* [8:0] */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0,
+	/* [17:9] */
+	.reg_mcusys_merge_ddr_en_mask_b = 0,
+	/* [19:18] */
+	.reg_dramc_md32_infra_req_mask_b = 3,
+	/* [21:20] */
+	.reg_dramc_md32_vrf18_req_mask_b = 3,
+	/* [23:22] */
+	.reg_dramc_md32_ddr_en_mask_b = 0,
+	/* [24] */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK2 */
+	/* [3:0] */
+	.reg_sc_sw2spm_wakeup_mask_b = 0,
+	/* [4] */
+	.reg_sc_adsp2spm_wakeup_mask_b = 0,
+	/* [8:5] */
+	.reg_sc_sspm2spm_wakeup_mask_b = 0,
+	/* [9] */
+	.reg_sc_scp2spm_wakeup_mask_b = 0,
+	/* [10] */
+	.reg_csyspwrup_ack_mask = 0,
+	/* [11] */
+	.reg_csyspwrup_req_mask = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	/* [31:0] */
+	.reg_wakeup_event_mask = 0xC1282203,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	/* [31:0] */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+struct spm_lp_scen idle_spm_lp = {
+	.pwrctrl = &idle_spm_pwr,
+};
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn)
+{
+	int ret = 0;
+	unsigned int src_req = 0U;
+
+	if (fn != NULL) {
+		fn(state_id, &idle_spm_lp, &src_req);
+	}
+
+	ret = spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
+
+	if (ret == 0) {
+		struct mt_lp_publish_event event = {
+			.id = MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+			.val.u32 = 0U,
+		};
+
+		MT_LP_PUBLISH_EVENT(&event);
+	}
+	return ret;
+}
+
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+				struct wake_status **status,
+				spm_idle_conduct_restore fn)
+{
+	struct mt_lp_publish_event event = {
+		.id = MT_LPM_PUBEVENTS_SYS_POWER_ON,
+		.val.u32 = 0U,
+	};
+
+	ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS);
+	spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
+
+	if (spm_unlikely(fn)) {
+		fn(state_id, &idle_spm_lp, *status);
+	}
+	MT_LP_PUBLISH_EVENT(&event);
+}

plat/mediatek/drivers/spm/mt8188/mt_spm_idle.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_IDLE_H
+#define MT_SPM_IDLE_H
+
+#include "mt_spm_internal.h"
+
+typedef int (*spm_idle_conduct)(int state_id,
+				struct spm_lp_scen *spm_lp,
+				unsigned int *resource_req);
+typedef int (*spm_idle_conduct_restore)(int state_id,
+					struct spm_lp_scen *spm_lp,
+					struct wake_status *status);
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn);
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+				struct wake_status **status,
+				spm_idle_conduct_restore fn);
+
+#endif

plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c

@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <drivers/spm/mt_spm_resource_req.h>
+#include "mt_spm.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+#define SPM_INIT_DONE_US (20) /* Simulation result */
+
+wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta)
+{
+	wake_reason_t wr = WR_UNKNOWN;
+
+	if (wakesta == NULL) {
+		return wr;
+	}
+
+	if (wakesta->is_abort != 0U) {
+		VERBOSE("SPM EARLY WAKE r12 = 0x%x, debug_flag = 0x%x 0x%x\n",
+			wakesta->tr.comm.r12,
+			wakesta->tr.comm.debug_flag, wakesta->tr.comm.debug_flag1);
+		VERBOSE("SPM EARLY WAKE sw_flag = 0x%x 0x%x b_sw_flag = 0x%x 0x%x\n",
+			wakesta->sw_flag0, wakesta->sw_flag1,
+			wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1);
+	}
+
+	if ((wakesta->tr.comm.r12 & R12_PCM_TIMER) != 0U) {
+
+		if ((wakesta->wake_misc & WAKE_MISC_PCM_TIMER_EVENT) != 0U) {
+			wr = WR_PCM_TIMER;
+		}
+	}
+
+	return wr;
+}
+
+void __spm_set_cpu_status(unsigned int cpu)
+{
+	if (cpu >= 8) {
+		ERROR("%s: error cpu number %d\n", __func__, cpu);
+		return;
+	}
+	mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu));
+	mmio_write_32(ROOT_CORE_ADDR, SPM_CPU0_PWR_CON + (cpu * 0x4) + 0x20000000);
+	/* Notify MCUPM to wake the target CPU up */
+	mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
+}
+
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage)
+{
+
+	uint8_t reg_spm_apsrc_req = (resource_usage & MT_SPM_DRAM_S0) ?
+				    1 : pwrctrl->reg_spm_apsrc_req;
+	uint8_t reg_spm_ddr_en_req = (resource_usage & MT_SPM_DRAM_S1) ?
+				     1 : pwrctrl->reg_spm_ddr_en_req;
+	uint8_t reg_spm_vrf18_req = (resource_usage & MT_SPM_SYSPLL) ?
+				    1 : pwrctrl->reg_spm_vrf18_req;
+	uint8_t reg_spm_infra_req = (resource_usage & MT_SPM_INFRA) ?
+				    1 : pwrctrl->reg_spm_infra_req;
+	uint8_t reg_spm_f26m_req  = (resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM)) ?
+				    1 : pwrctrl->reg_spm_f26m_req;
+
+	/* SPM_SRC_REQ */
+	mmio_write_32(SPM_SRC_REQ,
+		      ((reg_spm_apsrc_req & 0x1) << 0) |
+		      ((reg_spm_f26m_req & 0x1) << 1) |
+		      ((reg_spm_infra_req & 0x1) << 3) |
+		      ((reg_spm_vrf18_req & 0x1) << 4) |
+		      ((reg_spm_ddr_en_req & 0x1) << 7) |
+		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+}
+
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+	/* SPM_AP_STANDBY_CON */
+	mmio_write_32(SPM_AP_STANDBY_CON,
+		      ((pwrctrl->reg_wfi_op & 0x1) << 0) |
+		      ((pwrctrl->reg_wfi_type & 0x1) << 1) |
+		      ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+		      ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+		      ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+		      ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+		      ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+		      ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+	/* SPM_SRC_REQ */
+	mmio_write_32(SPM_SRC_REQ,
+		      ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+		      ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+		      ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+		      ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+		      ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+	/* SPM_SRC_MASK */
+	mmio_write_32(SPM_SRC_MASK,
+		      ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
+		      ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
+		      ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
+		      ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
+		      ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
+		      ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
+		      ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
+		      ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
+		      ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
+		      ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
+		      ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
+		      ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
+		      ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
+		      ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
+		      ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
+		      ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
+		      ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
+		      ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
+		      ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
+		      ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
+		      ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
+		      ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
+		      ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
+		      ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
+		      ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
+		      ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
+		      ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
+		      ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
+		      ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
+		      ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29) |
+		      ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 30) |
+		      ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC2_MASK */
+	mmio_write_32(SPM_SRC2_MASK,
+		      ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
+		      ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
+		      ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
+		      ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
+		      ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
+		      ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
+		      ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
+		      ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
+		      ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
+		      ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
+		      ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
+		      ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
+		      ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
+		      ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
+		      ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
+		      ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
+		      ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
+		      ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
+		      ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
+		      ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
+		      ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
+		      ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
+		      ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
+		      ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
+		      ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
+		      ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
+		      ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
+		      ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
+		      ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
+		      ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
+
+	/* SPM_SRC3_MASK */
+	mmio_write_32(SPM_SRC3_MASK,
+		      ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
+		      ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
+		      ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
+		      ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
+		      ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
+		      ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
+		      ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
+		      ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
+		      ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
+		      ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
+		      ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
+		      ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
+		      ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
+		      ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
+		      ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
+		      ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
+		      ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
+		      ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
+		      ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
+		      ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
+		      ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
+		      ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
+		      ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
+		      ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
+		      ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
+		      ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
+		      ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
+		      ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
+
+	/* SPM_SRC4_MASK */
+	mmio_write_32(SPM_SRC4_MASK,
+		      ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+		      ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
+		      ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 18) |
+		      ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 20) |
+		      ((pwrctrl->reg_dramc_md32_ddr_en_mask_b & 0x3) << 22) |
+		      ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 24));
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+		      ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+		      ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+}
+
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+	unsigned int val, mask;
+
+	/* toggle event counter clear */
+	mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+	/* toggle for reset SYS TIMER start point */
+	mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+
+	if (pwrctrl->timer_val_cust == 0U) {
+		val = (pwrctrl->timer_val != 0U) ? pwrctrl->timer_val : PCM_TIMER_MAX;
+	} else {
+		val = pwrctrl->timer_val_cust;
+	}
+
+	mmio_write_32(PCM_TIMER_VAL, val);
+	mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
+
+	/* unmask AP wakeup source */
+	if (pwrctrl->wake_src_cust == 0U) {
+		mask = pwrctrl->wake_src;
+	} else {
+		mask = pwrctrl->wake_src_cust;
+	}
+
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+	/* unmask SPM ISR (keep TWAM setting) */
+	mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
+
+	/* toggle event counter clear */
+	mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
+	/* toggle for reset SYS TIMER start point */
+	mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+}
+
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+	/* set PCM flags and data */
+	if (pwrctrl->pcm_flags_cust_clr != 0U) {
+		pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+	}
+	if (pwrctrl->pcm_flags_cust_set != 0U) {
+		pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+	}
+	if (pwrctrl->pcm_flags1_cust_clr != 0U) {
+		pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+	}
+	if (pwrctrl->pcm_flags1_cust_set != 0U) {
+		pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+	}
+
+	mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
+
+	mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
+
+	mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
+
+	mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
+}
+
+void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_status)
+{
+	/* get wakeup event */
+	wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);	/* backup of PCM_REG12_DATA */
+	wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_EXT_STA);
+	wakesta->tr.comm.raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+	wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+	wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
+	wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
+	wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);	/* backup of SPM_WAKEUP_MISC */
+
+	/* get sleep time */
+	wakesta->tr.comm.timer_out =
+		mmio_read_32(SPM_BK_PCM_TIMER);	/* backup of PCM_TIMER_OUT */
+
+	/* get other SYS and co-clock status */
+	wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
+	wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+	wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+	wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+	wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+	wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+	wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+	/* get debug flag for PCM execution check */
+	wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+	wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+	if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
+		wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
+						SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
+		mmio_write_32(PCM_WDT_LATCH_SPARE_0, wakesta->tr.comm.debug_flag);
+	}
+
+	/* get backup SW flag status */
+	wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);	/* SPM_SW_RSV_7 */
+	wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);	/* SPM_SW_RSV_8 */
+
+	/* get ISR status */
+	wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+
+	/* get SW flag status */
+	wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
+	wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+
+	/* check abort */
+	wakesta->is_abort = wakesta->tr.comm.debug_flag & DEBUG_ABORT_MASK;
+	wakesta->is_abort |= wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1;
+}
+
+void __spm_clean_after_wakeup(void)
+{
+	/*
+	 * Copy SPM_WAKEUP_STA to SPM_BK_WAKE_EVENT before clear SPM_WAKEUP_STA
+	 *
+	 * CPU dormant driver @kernel will copy edge-trig IRQ pending
+	 * (recorded @SPM_BK_WAKE_EVENT) to GIC
+	 */
+	mmio_write_32(SPM_BK_WAKE_EVENT, mmio_read_32(SPM_WAKEUP_STA) |
+		      mmio_read_32(SPM_BK_WAKE_EVENT));
+
+	/* clean CPU wakeup event */
+	mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0U);
+
+	/* clean wakeup event raw status (for edge trigger event) */
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK, 0xefffffff);	/* bit[28] for cpu wake up event */
+
+	/* clean ISR status (except TWAM) */
+	mmio_setbits_32(SPM_IRQ_MASK,  ISRM_ALL_EXC_TWAM);
+	mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+	mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void __spm_set_pcm_wdt(int en)
+{
+	/* enable PCM WDT (normal mode) to start count if needed */
+	if (en != 0) {
+		mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, SPM_REGWR_CFG_KEY);
+
+		if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
+			mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+		}
+		mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+		mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
+	} else {
+		mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, SPM_REGWR_CFG_KEY);
+	}
+}
+
+void __spm_send_cpu_wakeup_event(void)
+{
+	mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+	/* SPM will clear SPM_CPU_WAKEUP_EVENT */
+}
+
+void __spm_ext_int_wakeup_req_clr(void)
+{
+	mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
+
+	/* clear spm2mcupm wakeup interrupt status */
+	mmio_write_32(SPM2CPUEB_CON, 0);
+}
+
+void __spm_clean_before_wfi(void)
+{
+}
+
+void __spm_hw_s1_state_monitor(int en, unsigned int *status)
+{
+	unsigned int reg;
+
+	if (en != 0) {
+		mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_CLR_ALL,
+				   SPM_ACK_CHK_3_CON_EN);
+	} else {
+		reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+
+		if ((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) {
+			if (status != NULL) {
+				*status |= SPM_INTERNAL_STATUS_HW_S1;
+			}
+		}
+
+		mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
+				   (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL));
+	}
+}

plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h

@@ -0,0 +1,668 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_INTERNAL_H
+#define MT_SPM_INTERNAL_H
+
+#include <mt_spm.h>
+
+/* PCM_WDT_VAL */
+#define PCM_WDT_TIMEOUT		(30 * 32768)	/* 30s */
+/* PCM_TIMER_VAL */
+#define PCM_TIMER_MAX		(0xffffffff - PCM_WDT_TIMEOUT)
+
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0		BIT(0)
+#define PCM_PWRIO_EN_R7		BIT(7)
+#define PCM_RF_SYNC_R0		BIT(16)
+#define PCM_RF_SYNC_R6		BIT(22)
+#define PCM_RF_SYNC_R7		BIT(23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0		BIT(0)
+#define PCM_SW_INT1		BIT(1)
+#define PCM_SW_INT2		BIT(2)
+#define PCM_SW_INT3		BIT(3)
+#define PCM_SW_INT4		BIT(4)
+#define PCM_SW_INT5		BIT(5)
+#define PCM_SW_INT6		BIT(6)
+#define PCM_SW_INT7		BIT(7)
+#define PCM_SW_INT8		BIT(8)
+#define PCM_SW_INT9		BIT(9)
+#define PCM_SW_INT_ALL		(PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+				 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+				 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+				 PCM_SW_INT0)
+
+/* SPM_AP_STANDBY_CON */
+#define WFI_OP_AND		(1U)
+#define WFI_OP_OR		(0U)
+
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM		BIT(2)
+#define ISRM_PCM_RETURN		BIT(3)
+#define ISRM_RET_IRQ0		BIT(8)
+#define ISRM_RET_IRQ1		BIT(9)
+#define ISRM_RET_IRQ2		BIT(10)
+#define ISRM_RET_IRQ3		BIT(11)
+#define ISRM_RET_IRQ4		BIT(12)
+#define ISRM_RET_IRQ5		BIT(13)
+#define ISRM_RET_IRQ6		BIT(14)
+#define ISRM_RET_IRQ7		BIT(15)
+#define ISRM_RET_IRQ8		BIT(16)
+#define ISRM_RET_IRQ9		BIT(17)
+#define ISRM_RET_IRQ_AUX	((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+				 (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+				 (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+				 (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+				 (ISRM_RET_IRQ1))
+#define ISRM_ALL_EXC_TWAM	ISRM_RET_IRQ_AUX
+#define ISRM_ALL		(ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM		BIT(2)
+#define ISRS_PCM_RETURN		BIT(3)
+#define ISRC_TWAM		ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM	ISRS_PCM_RETURN
+#define ISRC_ALL		(ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP			(0x3FF)
+#define WAKE_MISC_DVFSRC_IRQ			DVFSRC_IRQ_LSB
+#define WAKE_MISC_REG_CPU_WAKEUP		SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
+#define WAKE_MISC_PCM_TIMER_EVENT		PCM_TIMER_EVENT_LSB
+#define WAKE_MISC_TWAM_IRQ_B			TWAM_IRQ_B_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET0		PMSR_IRQ_B_SET0_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET1		PMSR_IRQ_B_SET1_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET2		PMSR_IRQ_B_SET2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0		SPM_ACK_CHK_WAKEUP_0_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1		SPM_ACK_CHK_WAKEUP_1_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2		SPM_ACK_CHK_WAKEUP_2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3		SPM_ACK_CHK_WAKEUP_3_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL	SPM_ACK_CHK_WAKEUP_ALL_LSB
+#define WAKE_MISC_PMIC_IRQ_ACK			PMIC_IRQ_ACK_LSB
+#define WAKE_MISC_PMIC_SCP_IRQ			PMIC_SCP_IRQ_LSB
+
+/* MD32PCM ADDR for SPM code fetch */
+#define MD32PCM_BASE			(SPM_BASE + 0x0A00)
+#define MD32PCM_CFGREG_SW_RSTN		(MD32PCM_BASE + 0x0000)
+#define MD32PCM_DMA0_SRC		(MD32PCM_BASE + 0x0200)
+#define MD32PCM_DMA0_DST		(MD32PCM_BASE + 0x0204)
+#define MD32PCM_DMA0_WPPT		(MD32PCM_BASE + 0x0208)
+#define MD32PCM_DMA0_WPTO		(MD32PCM_BASE + 0x020C)
+#define MD32PCM_DMA0_COUNT		(MD32PCM_BASE + 0x0210)
+#define MD32PCM_DMA0_CON		(MD32PCM_BASE + 0x0214)
+#define MD32PCM_DMA0_START		(MD32PCM_BASE + 0x0218)
+#define MD32PCM_DMA0_RLCT		(MD32PCM_BASE + 0x0224)
+#define MD32PCM_INTC_IRQ_RAW_STA	(MD32PCM_BASE + 0x033C)
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
+			  SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
+			    SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
+			    SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
+			    SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
+			    SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
+			    SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
+			    SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+#define MCUPM_MBOX_WAKEUP_CPU (0x0C55FD10)
+
+struct pcm_desc {
+	const char *version;	/* PCM code version */
+	uint32_t *base;		/* binary array base */
+	uintptr_t base_dma;	/* dma addr of base */
+	uint32_t pmem_words;
+	uint32_t total_words;
+	uint32_t pmem_start;
+	uint32_t dmem_start;
+};
+
+struct pwr_ctrl {
+	/* for SPM */
+	uint32_t pcm_flags;
+	/* can override pcm_flags */
+	uint32_t pcm_flags_cust;
+	/* set bit of pcm_flags, after pcm_flags_cust */
+	uint32_t pcm_flags_cust_set;
+	/* clr bit of pcm_flags, after pcm_flags_cust */
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	/* can override pcm_flags1 */
+	uint32_t pcm_flags1_cust;
+	/* set bit of pcm_flags1, after pcm_flags1_cust */
+	uint32_t pcm_flags1_cust_set;
+	/* clr bit of pcm_flags1, after pcm_flags1_cust */
+	uint32_t pcm_flags1_cust_clr;
+	/* @ 1T 32K */
+	uint32_t timer_val;
+	/* @ 1T 32K, can override timer_val */
+	uint32_t timer_val_cust;
+	/* stress for dpidle */
+	uint32_t timer_val_ramp_en;
+	/* stress for suspend */
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	/* can override wake_src */
+	uint32_t wake_src_cust;
+	/* disable wdt in suspend */
+	uint8_t wdt_disable;
+
+	/* SPM_AP_STANDBY_CON */
+	/* [0] */
+	uint8_t reg_wfi_op;
+	/* [1] */
+	uint8_t reg_wfi_type;
+	/* [2] */
+	uint8_t reg_mp0_cputop_idle_mask;
+	/* [3] */
+	uint8_t reg_mp1_cputop_idle_mask;
+	/* [4] */
+	uint8_t reg_mcusys_idle_mask;
+	/* [25] */
+	uint8_t reg_md_apsrc_1_sel;
+	/* [26] */
+	uint8_t reg_md_apsrc_0_sel;
+	/* [29] */
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC_REQ */
+	/* [0] */
+	uint8_t reg_spm_apsrc_req;
+	/* [1] */
+	uint8_t reg_spm_f26m_req;
+	/* [3] */
+	uint8_t reg_spm_infra_req;
+	/* [4] */
+	uint8_t reg_spm_vrf18_req;
+	/* [7] */
+	uint8_t reg_spm_ddr_en_req;
+	/* [8] */
+	uint8_t reg_spm_dvfs_req;
+	/* [9] */
+	uint8_t reg_spm_sw_mailbox_req;
+	/* [10] */
+	uint8_t reg_spm_sspm_mailbox_req;
+	/* [11] */
+	uint8_t reg_spm_adsp_mailbox_req;
+	/* [12] */
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	/* [0] */
+	uint8_t reg_sspm_srcclkena_0_mask_b;
+	/* [1] */
+	uint8_t reg_sspm_infra_req_0_mask_b;
+	/* [2] */
+	uint8_t reg_sspm_apsrc_req_0_mask_b;
+	/* [3] */
+	uint8_t reg_sspm_vrf18_req_0_mask_b;
+	/* [4] */
+	uint8_t reg_sspm_ddr_en_0_mask_b;
+	/* [5] */
+	uint8_t reg_scp_srcclkena_mask_b;
+	/* [6] */
+	uint8_t reg_scp_infra_req_mask_b;
+	/* [7] */
+	uint8_t reg_scp_apsrc_req_mask_b;
+	/* [8] */
+	uint8_t reg_scp_vrf18_req_mask_b;
+	/* [9] */
+	uint8_t reg_scp_ddr_en_mask_b;
+	/* [10] */
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	/* [11] */
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	/* [12] */
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	/* [13] */
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	/* [14] */
+	uint8_t reg_audio_dsp_ddr_en_mask_b;
+	/* [15] */
+	uint8_t reg_apu_srcclkena_mask_b;
+	/* [16] */
+	uint8_t reg_apu_infra_req_mask_b;
+	/* [17] */
+	uint8_t reg_apu_apsrc_req_mask_b;
+	/* [18] */
+	uint8_t reg_apu_vrf18_req_mask_b;
+	/* [19] */
+	uint8_t reg_apu_ddr_en_mask_b;
+	/* [20] */
+	uint8_t reg_cpueb_srcclkena_mask_b;
+	/* [21] */
+	uint8_t reg_cpueb_infra_req_mask_b;
+	/* [22] */
+	uint8_t reg_cpueb_apsrc_req_mask_b;
+	/* [23] */
+	uint8_t reg_cpueb_vrf18_req_mask_b;
+	/* [24] */
+	uint8_t reg_cpueb_ddr_en_mask_b;
+	/* [25] */
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	/* [26] */
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	/* [27] */
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	/* [28] */
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	/* [29] */
+	uint8_t reg_bak_psri_ddr_en_mask_b;
+	/* [30] */
+	uint8_t reg_cam_ddren_req_mask_b;
+	/* [31] */
+	uint8_t reg_img_ddren_req_mask_b;
+
+	/* SPM_SRC2_MASK */
+	/* [0] */
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	/* [1] */
+	uint8_t reg_msdc0_infra_req_mask_b;
+	/* [2] */
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	/* [3] */
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	/* [4] */
+	uint8_t reg_msdc0_ddr_en_mask_b;
+	/* [5] */
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	/* [6] */
+	uint8_t reg_msdc1_infra_req_mask_b;
+	/* [7] */
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	/* [8] */
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	/* [9] */
+	uint8_t reg_msdc1_ddr_en_mask_b;
+	/* [10] */
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	/* [11] */
+	uint8_t reg_msdc2_infra_req_mask_b;
+	/* [12] */
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	/* [13] */
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	/* [14] */
+	uint8_t reg_msdc2_ddr_en_mask_b;
+	/* [15] */
+	uint8_t reg_ufs_srcclkena_mask_b;
+	/* [16] */
+	uint8_t reg_ufs_infra_req_mask_b;
+	/* [17] */
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	/* [18] */
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	/* [19] */
+	uint8_t reg_ufs_ddr_en_mask_b;
+	/* [20] */
+	uint8_t reg_usb_srcclkena_mask_b;
+	/* [21] */
+	uint8_t reg_usb_infra_req_mask_b;
+	/* [22] */
+	uint8_t reg_usb_apsrc_req_mask_b;
+	/* [23] */
+	uint8_t reg_usb_vrf18_req_mask_b;
+	/* [24] */
+	uint8_t reg_usb_ddr_en_mask_b;
+	/* [25] */
+	uint8_t reg_pextp_p0_srcclkena_mask_b;
+	/* [26] */
+	uint8_t reg_pextp_p0_infra_req_mask_b;
+	/* [27] */
+	uint8_t reg_pextp_p0_apsrc_req_mask_b;
+	/* [28] */
+	uint8_t reg_pextp_p0_vrf18_req_mask_b;
+	/* [29] */
+	uint8_t reg_pextp_p0_ddr_en_mask_b;
+
+	/* SPM_SRC3_MASK */
+	/* [0] */
+	uint8_t reg_pextp_p1_srcclkena_mask_b;
+	/* [1] */
+	uint8_t reg_pextp_p1_infra_req_mask_b;
+	/* [2] */
+	uint8_t reg_pextp_p1_apsrc_req_mask_b;
+	/* [3] */
+	uint8_t reg_pextp_p1_vrf18_req_mask_b;
+	/* [4] */
+	uint8_t reg_pextp_p1_ddr_en_mask_b;
+	/* [5] */
+	uint8_t reg_gce0_infra_req_mask_b;
+	/* [6] */
+	uint8_t reg_gce0_apsrc_req_mask_b;
+	/* [7] */
+	uint8_t reg_gce0_vrf18_req_mask_b;
+	/* [8] */
+	uint8_t reg_gce0_ddr_en_mask_b;
+	/* [9] */
+	uint8_t reg_gce1_infra_req_mask_b;
+	/* [10] */
+	uint8_t reg_gce1_apsrc_req_mask_b;
+	/* [11] */
+	uint8_t reg_gce1_vrf18_req_mask_b;
+	/* [12] */
+	uint8_t reg_gce1_ddr_en_mask_b;
+	/* [13] */
+	uint8_t reg_spm_srcclkena_reserved_mask_b;
+	/* [14] */
+	uint8_t reg_spm_infra_req_reserved_mask_b;
+	/* [15] */
+	uint8_t reg_spm_apsrc_req_reserved_mask_b;
+	/* [16] */
+	uint8_t reg_spm_vrf18_req_reserved_mask_b;
+	/* [17] */
+	uint8_t reg_spm_ddr_en_reserved_mask_b;
+	/* [18] */
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	/* [19] */
+	uint8_t reg_disp0_ddr_en_mask_b;
+	/* [20] */
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	/* [21] */
+	uint8_t reg_disp1_ddr_en_mask_b;
+	/* [22] */
+	uint8_t reg_disp2_apsrc_req_mask_b;
+	/* [23] */
+	uint8_t reg_disp2_ddr_en_mask_b;
+	/* [24] */
+	uint8_t reg_disp3_apsrc_req_mask_b;
+	/* [25] */
+	uint8_t reg_disp3_ddr_en_mask_b;
+	/* [26] */
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	/* [27] */
+	uint8_t reg_infrasys_ddr_en_mask_b;
+	/* [28] */
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	/* [29] */
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	/* [30] */
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	/* [31] */
+	uint8_t reg_cg_check_ddr_en_mask_b;
+
+	/* SPM_SRC4_MASK */
+	/* [8:0] */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	/* [17:9] */
+	uint32_t reg_mcusys_merge_ddr_en_mask_b;
+	/* [19:18] */
+	uint8_t reg_dramc_md32_infra_req_mask_b;
+	/* [21:20] */
+	uint8_t reg_dramc_md32_vrf18_req_mask_b;
+	/* [23:22] */
+	uint8_t reg_dramc_md32_ddr_en_mask_b;
+	/* [24] */
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK2 */
+	/* [3:0] */
+	uint8_t reg_sc_sw2spm_wakeup_mask_b;
+	/* [4] */
+	uint8_t reg_sc_adsp2spm_wakeup_mask_b;
+	/* [8:5] */
+	uint8_t reg_sc_sspm2spm_wakeup_mask_b;
+	/* [9] */
+	uint8_t reg_sc_scp2spm_wakeup_mask_b;
+	/* [10] */
+	uint8_t reg_csyspwrup_ack_mask;
+	/* [11] */
+	uint8_t reg_csyspwrup_req_mask;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	/* [31:0] */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	/* [31:0] */
+	uint32_t reg_ext_wakeup_event_mask;
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WDT_DISABLE,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDR_EN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_SSPM_SRCCLKENA_0_MASK_B,
+	PW_REG_SSPM_INFRA_REQ_0_MASK_B,
+	PW_REG_SSPM_APSRC_REQ_0_MASK_B,
+	PW_REG_SSPM_VRF18_REQ_0_MASK_B,
+	PW_REG_SSPM_DDR_EN_0_MASK_B,
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDR_EN_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDR_EN_MASK_B,
+	PW_REG_CPUEB_SRCCLKENA_MASK_B,
+	PW_REG_CPUEB_INFRA_REQ_MASK_B,
+	PW_REG_CPUEB_APSRC_REQ_MASK_B,
+	PW_REG_CPUEB_VRF18_REQ_MASK_B,
+	PW_REG_CPUEB_DDR_EN_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDR_EN_MASK_B,
+	PW_REG_CAM_DDREN_REQ_MASK_B,
+	PW_REG_IMG_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDR_EN_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDR_EN_MASK_B,
+	PW_REG_MSDC2_SRCCLKENA_MASK_B,
+	PW_REG_MSDC2_INFRA_REQ_MASK_B,
+	PW_REG_MSDC2_APSRC_REQ_MASK_B,
+	PW_REG_MSDC2_VRF18_REQ_MASK_B,
+	PW_REG_MSDC2_DDR_EN_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDR_EN_MASK_B,
+	PW_REG_USB_SRCCLKENA_MASK_B,
+	PW_REG_USB_INFRA_REQ_MASK_B,
+	PW_REG_USB_APSRC_REQ_MASK_B,
+	PW_REG_USB_VRF18_REQ_MASK_B,
+	PW_REG_USB_DDR_EN_MASK_B,
+	PW_REG_PEXTP_P0_SRCCLKENA_MASK_B,
+	PW_REG_PEXTP_P0_INFRA_REQ_MASK_B,
+	PW_REG_PEXTP_P0_APSRC_REQ_MASK_B,
+	PW_REG_PEXTP_P0_VRF18_REQ_MASK_B,
+	PW_REG_PEXTP_P0_DDR_EN_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_PEXTP_P1_SRCCLKENA_MASK_B,
+	PW_REG_PEXTP_P1_INFRA_REQ_MASK_B,
+	PW_REG_PEXTP_P1_APSRC_REQ_MASK_B,
+	PW_REG_PEXTP_P1_VRF18_REQ_MASK_B,
+	PW_REG_PEXTP_P1_DDR_EN_MASK_B,
+	PW_REG_GCE0_INFRA_REQ_MASK_B,
+	PW_REG_GCE0_APSRC_REQ_MASK_B,
+	PW_REG_GCE0_VRF18_REQ_MASK_B,
+	PW_REG_GCE0_DDR_EN_MASK_B,
+	PW_REG_GCE1_INFRA_REQ_MASK_B,
+	PW_REG_GCE1_APSRC_REQ_MASK_B,
+	PW_REG_GCE1_VRF18_REQ_MASK_B,
+	PW_REG_GCE1_DDR_EN_MASK_B,
+	PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+	PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDR_EN_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDR_EN_MASK_B,
+	PW_REG_DISP2_APSRC_REQ_MASK_B,
+	PW_REG_DISP2_DDR_EN_MASK_B,
+	PW_REG_DISP3_APSRC_REQ_MASK_B,
+	PW_REG_DISP3_DDR_EN_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDR_EN_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDR_EN_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+	PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_DDR_EN_MASK_B,
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK2 */
+	PW_REG_SC_SW2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRUP_ACK_MASK,
+	PW_REG_CSYSPWRUP_REQ_MASK,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+	PW_MAX_COUNT,
+};
+
+/* spm_internal.c internal status */
+#define SPM_INTERNAL_STATUS_HW_S1	BIT(0)
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG	(0x800)
+/* BIT[0]: SW_EN, BIT[4]: STA_EN, BIT[8]: HW_EN */
+#define SPM_ACK_CHK_3_CON_EN		(0x110)
+#define SPM_ACK_CHK_3_CON_CLR_ALL	(0x2)
+/* BIT[15]: RESULT */
+#define SPM_ACK_CHK_3_CON_RESULT	(0x8000)
+
+struct wake_status_trace_comm {
+	uint32_t debug_flag;	/* PCM_WDT_LATCH_SPARE_0 */
+	uint32_t debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	uint32_t timer_out;	/* SPM_SW_RSV_6*/
+	uint32_t b_sw_flag0;	/* SPM_SW_RSV_7 */
+	uint32_t b_sw_flag1;	/* SPM_SW_RSV_7 */
+	uint32_t r12;		/* SPM_SW_RSV_0 */
+	uint32_t r13;		/* PCM_REG13_DATA */
+	uint32_t req_sta0;	/* SRC_REQ_STA_0 */
+	uint32_t req_sta1;	/* SRC_REQ_STA_1 */
+	uint32_t req_sta2;	/* SRC_REQ_STA_2 */
+	uint32_t req_sta3;	/* SRC_REQ_STA_3 */
+	uint32_t req_sta4;	/* SRC_REQ_STA_4 */
+	uint32_t raw_sta;	/* SPM_WAKEUP_STA */
+	uint32_t times_h;	/* timestamp high bits */
+	uint32_t times_l;	/* timestamp low bits */
+	uint32_t resumetime;	/* timestamp low bits */
+};
+
+struct wake_status_trace {
+	struct wake_status_trace_comm comm;
+};
+
+struct wake_status {
+	struct wake_status_trace tr;
+	uint32_t r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	uint32_t raw_ext_sta;		/* SPM_WAKEUP_EXT_STA */
+	uint32_t md32pcm_wakeup_sta;	/* MD32PCM_WAKEUP_STA */
+	uint32_t md32pcm_event_sta;	/* MD32PCM_EVENT_STA */
+	uint32_t wake_misc;		/* SPM_SW_RSV_5 */
+	uint32_t idle_sta;		/* SUBSYS_IDLE_STA */
+	uint32_t sw_flag0;		/* SPM_SW_FLAG_0 */
+	uint32_t sw_flag1;		/* SPM_SW_FLAG_1 */
+	uint32_t isr;			/* SPM_IRQ_STA */
+	uint32_t log_index;
+	uint32_t is_abort;
+};
+
+struct spm_lp_scen {
+	struct pcm_desc *pcmdesc;
+	struct pwr_ctrl *pwrctrl;
+};
+
+void __spm_set_cpu_status(unsigned int cpu);
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage);
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
+void __spm_send_cpu_wakeup_event(void);
+void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_status);
+void __spm_clean_after_wakeup(void);
+wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta);
+void __spm_set_pcm_wdt(int en);
+void __spm_ext_int_wakeup_req_clr(void);
+void __spm_hw_s1_state_monitor(int en, unsigned int *status);
+
+static inline void spm_hw_s1_state_monitor_resume(void)
+{
+	__spm_hw_s1_state_monitor(1, NULL);
+}
+
+static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
+{
+	__spm_hw_s1_state_monitor(0, status);
+}
+
+void __spm_clean_before_wfi(void);
+
+#endif /* MT_SPM_INTERNAL */

plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.c

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+
+#include <lib/pm/mtk_pm.h>
+#include "mt_spm.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+/* BIT operation */
+#define _BITS_(h, l, v) ((GENMASK(h, l) & ((v) << (l))))
+
+/* PMIC_WRAP */
+#define VCORE_BASE_UV			(40000) /* PMIC MT6359 */
+#define VOLT_TO_PMIC_VAL(volt)		(((volt) - VCORE_BASE_UV + 625 - 1) / 625)
+
+#define NR_PMIC_WRAP_CMD		(NR_IDX_ALL)
+#define SPM_DATA_SHIFT			(16)
+
+#define BUCK_VGPU11_ELR0		(0x15B4)
+#define TOP_SPI_CON0			(0x0456)
+#define BUCK_TOP_CON1			(0x1443) /* PMIC MT6315 */
+#define TOP_CON				(0x0013) /* PMIC MT6315 */
+#define TOP_DIG_WPK			(0x03a9)
+#define TOP_CON_LOCK			(0x03a8)
+#define TOP_CLK_CON0			(0x0134) /* PMIC MT6359*/
+
+struct pmic_wrap_cmd {
+	uint32_t cmd_addr;
+	uint32_t cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+	enum pmic_wrap_phase_id phase;
+	struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+	struct {
+		struct {
+			uint32_t cmd_addr;
+			uint32_t cmd_wdata;
+		} _[NR_PMIC_WRAP_CMD];
+		const int nr_idx;
+	} set[NR_PMIC_WRAP_PHASE];
+};
+
+static struct pmic_wrap_setting pw = {
+	.phase = NR_PMIC_WRAP_PHASE,	/* invalid setting for init */
+	.addr = {{0, 0} },
+	.set[PMIC_WRAP_PHASE_ALLINONE] = {
+		._[CMD_0]	= {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(75000)),},
+		._[CMD_1]	= {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(65000)),},
+		._[CMD_2]	= {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(60000)),},
+		._[CMD_3]	= {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(55000)),},
+		._[CMD_4]	= {TOP_SPI_CON0, _BITS_(0, 0, 1),},
+		._[CMD_5]	= {TOP_SPI_CON0, _BITS_(0, 0, 0),},
+		._[CMD_6]	= {BUCK_TOP_CON1, 0x0,},	/* MT6315-3: VMD NO LP */
+		._[CMD_7]	= {BUCK_TOP_CON1, 0xF,},	/* MT6315-3: VMD LP */
+		._[CMD_8]	= {TOP_CON, 0x3,},		/* MT6315-3: PMIC NO LP */
+		._[CMD_9]	= {TOP_CON, 0x0,},		/* MT6315-3: PMIC LP */
+		._[CMD_10]	= {TOP_DIG_WPK, 0x63,},		/* MT6315-2: PMIC_CON_DIG_WPK */
+		._[CMD_11]	= {TOP_CON_LOCK, 0x15,},	/* MT6315-2: PMIC_CON_UNLOCK */
+		._[CMD_12]	= {TOP_DIG_WPK, 0x0,},		/* MT6315-2: PMIC_CON_DIG_WPK */
+		._[CMD_13]	= {TOP_CON_LOCK, 0x0,},		/* MT6315-2: PMIC_CON_LOCK */
+		._[CMD_14]	= {TOP_CLK_CON0, 0x0040,},	/* MT6359: 6359_LDO_SW_SEL_H */
+		._[CMD_15]	= {TOP_CLK_CON0, 0x0000,},	/* MT6359: 6359_LDO_SW_SEL_L */
+		.nr_idx = NR_IDX_ALL,
+	},
+};
+
+void _mt_spm_pmic_table_init(void)
+{
+	struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+		{ (uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0, },
+		{ (uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1, },
+		{ (uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2, },
+		{ (uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3, },
+		{ (uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4, },
+		{ (uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5, },
+		{ (uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6, },
+		{ (uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7, },
+		{ (uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8, },
+		{ (uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9, },
+		{ (uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10, },
+		{ (uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11, },
+		{ (uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12, },
+		{ (uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13, },
+		{ (uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14, },
+		{ (uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15, },
+	};
+
+	memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+	int idx;
+
+	if ((phase >= NR_PMIC_WRAP_PHASE) || (pw.phase == phase)) {
+		return;
+	}
+
+	if (pw.addr[0].cmd_addr == 0) {
+		_mt_spm_pmic_table_init();
+	}
+
+	pw.phase = phase;
+
+	mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+	for (idx = 0; idx < pw.set[phase].nr_idx; idx++) {
+		mmio_write_32(pw.addr[idx].cmd_addr,
+			      (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) |
+			      (pw.set[phase]._[idx].cmd_wdata));
+	}
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx,
+			      unsigned int cmd_wdata)
+{
+	/* just set wdata value */
+	if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) {
+		return;
+	}
+
+	pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
+
+	mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+	if (pw.phase == phase) {
+		mmio_write_32(pw.addr[idx].cmd_addr,
+			      (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | cmd_wdata);
+	}
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx)
+{
+	/* just get wdata value */
+	if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) {
+		return 0;
+	}
+
+	return pw.set[phase]._[idx].cmd_wdata;
+}

plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+
+#ifndef MT_SPM_PMIC_WRAP_H
+#define MT_SPM_PMIC_WRAP_H
+
+enum pmic_wrap_phase_id {
+	PMIC_WRAP_PHASE_ALLINONE = 0,
+	NR_PMIC_WRAP_PHASE,
+};
+
+/* IDX mapping */
+enum {
+	CMD_0 = 0,	/* PMIC_WRAP_PHASE_ALLINONE */
+	CMD_1,
+	CMD_2,
+	CMD_3,
+	CMD_4,
+	CMD_5,
+	CMD_6,
+	CMD_7,
+	CMD_8,
+	CMD_9,
+	CMD_10,
+	CMD_11,
+	CMD_12,
+	CMD_13,
+	CMD_14,
+	CMD_15,
+	NR_IDX_ALL,
+};
+
+/* APIs */
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx,
+			      unsigned int cmd_wdata);
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx);
+void mt_spm_dump_pmic_warp_reg(void);
+
+#endif /* MT_SPM_PMIC_WRAP_H */

plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.c

@@ -0,0 +1,429 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+#include <drivers/uart.h>
+#endif
+#include <lib/mmio.h>
+#ifndef MTK_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+#include <constraints/mt_spm_rc_internal.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <pcm_def.h>
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG \
+	(SPM_FLAG_DISABLE_INFRA_PDN | \
+	 SPM_FLAG_DISABLE_VCORE_DVS | \
+	 SPM_FLAG_DISABLE_VCORE_DFS | \
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+	 SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG1	(SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+#define SPM_SUSPEND_PCM_FLAG \
+	(SPM_FLAG_DISABLE_VCORE_DVS | \
+	 SPM_FLAG_DISABLE_VCORE_DFS | \
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+	 SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_PCM_FLAG1	(SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+/* Suspend spm power control */
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__ ( \
+	(R12_PCM_TIMER) | \
+	(R12_KP_IRQ_B) | \
+	(R12_APWDT_EVENT_B) | \
+	(R12_MSDC_WAKEUP_B) | \
+	(R12_EINT_EVENT_B) | \
+	(R12_SBD_INTR_WAKEUP_B) | \
+	(R12_SSPM2SPM_WAKEUP_B) | \
+	(R12_SCP2SPM_WAKEUP_B) | \
+	(R12_ADSP2SPM_WAKEUP_B) | \
+	(R12_USBX_CDSC_B) | \
+	(R12_USBX_POWERDWN_B) | \
+	(R12_SYS_TIMER_EVENT_B) | \
+	(R12_EINT_EVENT_SECURE_B) | \
+	(R12_ECE_INT_HDMI_B) | \
+	(R12_SYS_CIRQ_IRQ_B) | \
+	(R12_PCIE_WAKEUPEVENT_B) | \
+	(R12_SPM_CPU_WAKEUPEVENT_B) | \
+	(R12_APUSYS_WAKE_HOST_B))
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND	(__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND	(__WAKE_SRC_FOR_SUSPEND_COMMON__ | R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl suspend_ctrl = {
+	.wake_src = WAKE_SRC_FOR_SUSPEND,
+
+	/* SPM_AP_STANDBY_CON */
+	/* [0] */
+	.reg_wfi_op = 0,
+	/* [1] */
+	.reg_wfi_type = 0,
+	/* [2] */
+	.reg_mp0_cputop_idle_mask = 0,
+	/* [3] */
+	.reg_mp1_cputop_idle_mask = 0,
+	/* [4] */
+	.reg_mcusys_idle_mask = 0,
+	/* [25] */
+	.reg_md_apsrc_1_sel = 0,
+	/* [26] */
+	.reg_md_apsrc_0_sel = 0,
+	/* [29] */
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC_REQ */
+	/* [0] */
+	.reg_spm_apsrc_req = 0,
+	/* [1] */
+	.reg_spm_f26m_req = 0,
+	/* [3] */
+	.reg_spm_infra_req = 0,
+	/* [4] */
+	.reg_spm_vrf18_req = 0,
+	/* [7] */
+	.reg_spm_ddr_en_req = 0,
+	/* [8] */
+	.reg_spm_dvfs_req = 0,
+	/* [9] */
+	.reg_spm_sw_mailbox_req = 0,
+	/* [10] */
+	.reg_spm_sspm_mailbox_req = 0,
+	/* [11] */
+	.reg_spm_adsp_mailbox_req = 0,
+	/* [12] */
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	/* [0] */
+	.reg_sspm_srcclkena_0_mask_b = 1,
+	/* [1] */
+	.reg_sspm_infra_req_0_mask_b = 1,
+	/* [2] */
+	.reg_sspm_apsrc_req_0_mask_b = 0,
+	/* [3] */
+	.reg_sspm_vrf18_req_0_mask_b = 0,
+	/* [4] */
+	.reg_sspm_ddr_en_0_mask_b = 0,
+	/* [5] */
+	.reg_scp_srcclkena_mask_b = 1,
+	/* [6] */
+	.reg_scp_infra_req_mask_b = 1,
+	/* [7] */
+	.reg_scp_apsrc_req_mask_b = 1,
+	/* [8] */
+	.reg_scp_vrf18_req_mask_b = 1,
+	/* [9] */
+	.reg_scp_ddr_en_mask_b = 1,
+	/* [10] */
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	/* [11] */
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	/* [12] */
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	/* [13] */
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	/* [14] */
+	.reg_audio_dsp_ddr_en_mask_b = 1,
+	/* [15] */
+	.reg_apu_srcclkena_mask_b = 1,
+	/* [16] */
+	.reg_apu_infra_req_mask_b = 1,
+	/* [17] */
+	.reg_apu_apsrc_req_mask_b = 0,
+	/* [18] */
+	.reg_apu_vrf18_req_mask_b = 1,
+	/* [19] */
+	.reg_apu_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_cpueb_srcclkena_mask_b = 1,
+	/* [21] */
+	.reg_cpueb_infra_req_mask_b = 1,
+	/* [22] */
+	.reg_cpueb_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_cpueb_vrf18_req_mask_b = 1,
+	/* [24] */
+	.reg_cpueb_ddr_en_mask_b = 1,
+	/* [25] */
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	/* [26] */
+	.reg_bak_psri_infra_req_mask_b = 0,
+	/* [27] */
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	/* [28] */
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	/* [29] */
+	.reg_bak_psri_ddr_en_mask_b = 0,
+	/* [30] */
+	.reg_cam_ddren_req_mask_b = 0,
+	/* [31] */
+	.reg_img_ddren_req_mask_b = 0,
+
+	/* SPM_SRC2_MASK */
+	/* [0] */
+	.reg_msdc0_srcclkena_mask_b = 1,
+	/* [1] */
+	.reg_msdc0_infra_req_mask_b = 1,
+	/* [2] */
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	/* [3] */
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	/* [4] */
+	.reg_msdc0_ddr_en_mask_b = 1,
+	/* [5] */
+	.reg_msdc1_srcclkena_mask_b = 1,
+	/* [6] */
+	.reg_msdc1_infra_req_mask_b = 1,
+	/* [7] */
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	/* [8] */
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	/* [9] */
+	.reg_msdc1_ddr_en_mask_b = 1,
+	/* [10] */
+	.reg_msdc2_srcclkena_mask_b = 1,
+	/* [11] */
+	.reg_msdc2_infra_req_mask_b = 1,
+	/* [12] */
+	.reg_msdc2_apsrc_req_mask_b = 1,
+	/* [13] */
+	.reg_msdc2_vrf18_req_mask_b = 1,
+	/* [14] */
+	.reg_msdc2_ddr_en_mask_b = 1,
+	/* [15] */
+	.reg_ufs_srcclkena_mask_b = 1,
+	/* [16] */
+	.reg_ufs_infra_req_mask_b = 1,
+	/* [17] */
+	.reg_ufs_apsrc_req_mask_b = 1,
+	/* [18] */
+	.reg_ufs_vrf18_req_mask_b = 1,
+	/* [19] */
+	.reg_ufs_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_usb_srcclkena_mask_b = 1,
+	/* [21] */
+	.reg_usb_infra_req_mask_b = 1,
+	/* [22] */
+	.reg_usb_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_usb_vrf18_req_mask_b = 1,
+	/* [24] */
+	.reg_usb_ddr_en_mask_b = 1,
+	/* [25] */
+	.reg_pextp_p0_srcclkena_mask_b = 1,
+	/* [26] */
+	.reg_pextp_p0_infra_req_mask_b = 1,
+	/* [27] */
+	.reg_pextp_p0_apsrc_req_mask_b = 1,
+	/* [28] */
+	.reg_pextp_p0_vrf18_req_mask_b = 1,
+	/* [29] */
+	.reg_pextp_p0_ddr_en_mask_b = 1,
+
+	/* SPM_SRC3_MASK */
+	/* [0] */
+	.reg_pextp_p1_srcclkena_mask_b = 1,
+	/* [1] */
+	.reg_pextp_p1_infra_req_mask_b = 1,
+	/* [2] */
+	.reg_pextp_p1_apsrc_req_mask_b = 1,
+	/* [3] */
+	.reg_pextp_p1_vrf18_req_mask_b = 1,
+	/* [4] */
+	.reg_pextp_p1_ddr_en_mask_b = 1,
+	/* [5] */
+	.reg_gce0_infra_req_mask_b = 1,
+	/* [6] */
+	.reg_gce0_apsrc_req_mask_b = 1,
+	/* [7] */
+	.reg_gce0_vrf18_req_mask_b = 1,
+	/* [8] */
+	.reg_gce0_ddr_en_mask_b = 1,
+	/* [9] */
+	.reg_gce1_infra_req_mask_b = 1,
+	/* [10] */
+	.reg_gce1_apsrc_req_mask_b = 1,
+	/* [11] */
+	.reg_gce1_vrf18_req_mask_b = 1,
+	/* [12] */
+	.reg_gce1_ddr_en_mask_b = 1,
+	/* [13] */
+	.reg_spm_srcclkena_reserved_mask_b = 1,
+	/* [14] */
+	.reg_spm_infra_req_reserved_mask_b = 1,
+	/* [15] */
+	.reg_spm_apsrc_req_reserved_mask_b = 1,
+	/* [16] */
+	.reg_spm_vrf18_req_reserved_mask_b = 1,
+	/* [17] */
+	.reg_spm_ddr_en_reserved_mask_b = 1,
+	/* [18] */
+	.reg_disp0_apsrc_req_mask_b = 1,
+	/* [19] */
+	.reg_disp0_ddr_en_mask_b = 1,
+	/* [20] */
+	.reg_disp1_apsrc_req_mask_b = 1,
+	/* [21] */
+	.reg_disp1_ddr_en_mask_b = 1,
+	/* [22] */
+	.reg_disp2_apsrc_req_mask_b = 1,
+	/* [23] */
+	.reg_disp2_ddr_en_mask_b = 1,
+	/* [24] */
+	.reg_disp3_apsrc_req_mask_b = 1,
+	/* [25] */
+	.reg_disp3_ddr_en_mask_b = 1,
+	/* [26] */
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	/* [27] */
+	.reg_infrasys_ddr_en_mask_b = 1,
+
+	/* [28] */
+	.reg_cg_check_srcclkena_mask_b = 1,
+	/* [29] */
+	.reg_cg_check_apsrc_req_mask_b = 1,
+	/* [30] */
+	.reg_cg_check_vrf18_req_mask_b = 1,
+	/* [31] */
+	.reg_cg_check_ddr_en_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	/* [8:0] */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0,
+	/* [17:9] */
+	.reg_mcusys_merge_ddr_en_mask_b = 0,
+	/* [19:18] */
+	.reg_dramc_md32_infra_req_mask_b = 3,
+	/* [21:20] */
+	.reg_dramc_md32_vrf18_req_mask_b = 3,
+	/* [23:22] */
+	.reg_dramc_md32_ddr_en_mask_b = 0,
+	/* [24] */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK2 */
+	/* [3:0] */
+	.reg_sc_sw2spm_wakeup_mask_b = 0,
+	/* [4] */
+	.reg_sc_adsp2spm_wakeup_mask_b = 0,
+	/* [8:5] */
+	.reg_sc_sspm2spm_wakeup_mask_b = 0,
+	/* [9] */
+	.reg_sc_scp2spm_wakeup_mask_b = 0,
+	/* [10] */
+	.reg_csyspwrup_ack_mask = 0,
+	/* [11] */
+	.reg_csyspwrup_req_mask = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	/* [31:0] */
+	.reg_wakeup_event_mask = 0xC1382213,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	/* [31:0] */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+	/*sw flag setting */
+	.pcm_flags = SPM_SUSPEND_PCM_FLAG,
+	.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
+};
+
+struct spm_lp_scen __spm_suspend = {
+	.pwrctrl = &suspend_ctrl,
+};
+
+int mt_spm_suspend_mode_set(int mode, void *prv)
+{
+	if (mode == MT_SPM_SUSPEND_SLEEP) {
+		suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
+		suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
+	} else {
+		suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
+		suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
+	}
+	return 0;
+}
+
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, unsigned int reosuce_req)
+{
+	int ret = 0;
+
+	/* if FMAudio, ADSP is active, change to sleep suspend mode */
+	if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+		mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP, NULL);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_PERI_ON) != 0U) {
+		suspend_ctrl.pcm_flags |= SPM_FLAG_PERI_ON_IN_SUSPEND;
+	} else {
+		suspend_ctrl.pcm_flags &= ~SPM_FLAG_PERI_ON_IN_SUSPEND;
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_INFRA_ON) != 0U) {
+		suspend_ctrl.pcm_flags |= SPM_FLAG_DISABLE_INFRA_PDN;
+	} else {
+		suspend_ctrl.pcm_flags &= ~SPM_FLAG_DISABLE_INFRA_PDN;
+	}
+
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+	/* Notify UART to sleep */
+	mtk_uart_save();
+#endif
+
+	ret = spm_conservation(state_id, ext_opand, &__spm_suspend, reosuce_req);
+	if (ret == 0) {
+		struct mt_lp_publish_event event = {
+			.id = MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+			.val.u32 = 0U,
+		};
+
+		MT_LP_SUSPEND_PUBLISH_EVENT(&event);
+	}
+	return ret;
+}
+
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, struct wake_status **status)
+{
+	struct mt_lp_publish_event event = {
+		.id = MT_LPM_PUBEVENTS_SYS_POWER_ON,
+		.val.u32 = 0U,
+	};
+
+	struct wake_status *st = NULL;
+
+	spm_conservation_finish(state_id, ext_opand, &__spm_suspend, &st);
+
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+	/* Notify UART to wakeup */
+	mtk_uart_restore();
+#endif
+
+	/* If FMAudio, ADSP is active, change back to suspend mode and counting in resume */
+	if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+		mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN, NULL);
+	}
+
+	if (status != NULL) {
+		*status = st;
+	}
+	MT_LP_SUSPEND_PUBLISH_EVENT(&event);
+}

plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SUSPEND_H
+#define MT_SPM_SUSPEND_H
+
+#include <mt_spm_internal.h>
+
+struct suspend_dbg_ctrl {
+	uint32_t sleep_suspend_cnt;
+};
+
+enum mt_spm_suspend_mode {
+	MT_SPM_SUSPEND_SYSTEM_PDN = 0,
+	MT_SPM_SUSPEND_SLEEP,
+};
+
+int mt_spm_suspend_mode_set(int mode, void *prv);
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, unsigned int reosuce_req);
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, struct wake_status **status);
+
+#endif

plat/mediatek/drivers/spm/mt8188/pcm_def.h

@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCM_DEF_H
+#define PCM_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF                      (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN               (1U << 1)
+#define R0_SC_MEM_CK_OFF                      (1U << 2)
+#define R0_SC_AXI_CK_OFF                      (1U << 3)
+#define R0_SC_DR_SRAM_LOAD                    (1U << 4)
+#define R0_SC_MD26M_CK_OFF                    (1U << 5)
+#define R0_SC_DPY_MODE_SW                     (1U << 6)
+#define R0_SC_DMSUS_OFF                       (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN                  (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE                 (1U << 9)
+#define R0_SC_MPLLOUT_OFF                     (1U << 10)
+#define R0_SC_TX_TRACKING_DIS                 (1U << 11)
+#define R0_SC_DPY_DLL_EN                      (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN                   (1U << 13)
+#define R0_SC_DPY_VREF_EN                     (1U << 14)
+#define R0_SC_PHYPLL_EN                       (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN                 (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE                 (1U << 17)
+#define R0_SC_MPLL_OFF                        (1U << 18)
+#define R0_SC_SHU_RESTORE                     (1U << 19)
+#define R0_SC_CKSQ0_OFF                       (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH         (1U << 21)
+#define R0_SC_DR_SHU_EN                       (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP                  (1U << 23)
+#define R0_SC_MPLL_S_OFF                      (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN             (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN                   (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN                  (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW                  (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW                 (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0                   (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1                   (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ                    (1U << 0)
+#define R7_EMI_CLK_OFF_REQ                    (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ                (1U << 2)
+#define R7_SPM_CK_UPDATE                      (1U << 3)
+#define R7_SPM_CK_SEL0                        (1U << 4)
+#define R7_SPM_CK_SEL1                        (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ             (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL                  (1U << 7)
+#define R7_SC_26M_CK_SEL                      (1U << 8)
+#define R7_PCM_TIMER_SET                      (1U << 9)
+#define R7_PCM_TIMER_CLR                      (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ              (1U << 11)
+#define R7_CSYSPWRUPACK                       (1U << 12)
+#define R7_PCM_IM_SLP_EN                      (1U << 13)
+#define R7_SRCCLKENO0                         (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE                  (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK             (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL              (1U << 17)
+#define R7_SC_AXI_DCM_DIS                     (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM                   (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN                  (1U << 20)
+#define R7_SRCCLKENO1                         (1U << 21)
+#define R7_PCM_WDT_KICK_P                     (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC              (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM                 (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM           (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN                    (1U << 26)
+#define R7_FORCE_F26M_WAKE                    (1U << 27)
+#define R7_FORCE_APSRC_WAKE                   (1U << 28)
+#define R7_FORCE_INFRA_WAKE                   (1U << 29)
+#define R7_FORCE_VRF18_WAKE                   (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK            (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER                         (1U << 0)
+#define R12_TWAM_IRQ_B                        (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT1_EVENT_B                   (1U << 4)
+#define R12_MSDC_WAKEUP_B                     (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_NOT_USED_7                        (1U << 7)
+#define R12_SBD_INTR_WAKEUP_B                 (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B                 (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B                  (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B                 (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B                  (1U << 13)
+#define R12_USBX_CDSC_B                       (1U << 14)
+#define R12_USBX_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_ECE_INT_HDMI_B                    (1U << 18)
+#define R12_I2C_IRQ_B                         (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERM_CTRL_EVENT_B                (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_NOT_USED_23                       (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_NOT_USED_25                       (1U << 25)
+#define R12_PCIE_WAKEUPEVENT_B                (1U << 26)
+#define R12_SEJ_EVENT_B                       (1U << 27)
+#define R12_SPM_CPU_WAKEUPEVENT_B             (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B                (1U << 29)
+#define R12_NOT_USED_30                       (1U << 30)
+#define R12_NOT_USED_31                       (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_MCU_PM_WFI                     (1U << 11)
+#define R12EXT_SSPM_IDLE                      (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE           (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK          (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK         (1U << 20)
+#define R12EXT_VS1_TRIGGER                    (1U << 21)
+#define R12EXT_VS2_TRIGGER                    (1U << 22)
+#define R12EXT_COROSS_REQ_APU                 (1U << 23)
+#define R12EXT_CROSS_REQ_L3                   (1U << 24)
+#define R12EXT_DDR_PST_ACK                    (1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_SRCCLKENA_0                    (1U << 2)
+#define R13_MD_APSRC_REQ_0                    (1U << 3)
+#define R13_CONN_DDR_EN                       (1U << 4)
+#define R13_MD_SRCCLKENA_1                    (1U << 5)
+#define R13_SSPM_SRCCLKENA                    (1U << 6)
+#define R13_SSPM_APSRC_REQ                    (1U << 7)
+#define R13_MD1_STATE                         (1U << 8)
+#define R13_BIT9                              (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_SSPM_STATE                        (1U << 11)
+#define R13_MD_DDR_EN_0                       (1U << 12)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCLKENA                    (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL                (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL          (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL            (1U << 21)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL             (1U << 23)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL           (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0              (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL       (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL        (1U << 29)
+#define R13_MD_VRF18_REQ_0                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+
+#endif /* PCM_DEF_H */

plat/mediatek/drivers/spm/mt8188/rules.mk

@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+MODULE := spm_${MTK_SOC}
+
+define GET_UPPER_DIR
+$(shell dirname ${LOCAL_DIR})
+endef
+UPPER_DIR := $(call GET_UPPER_DIR)
+
+MT_SPM_FEATURE_SUPPORT := y
+MT_SPM_CIRQ_FEATURE_SUPPORT := n
+MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT := n
+MT_SPM_SSPM_NOTIFIER_SUPPORT := y
+MT_SPM_UART_SUSPEND_SUPPORT := n
+MT_SPM_RGU_SUPPORT := n
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/mt_spm.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_conservation.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_internal.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_pmic_wrap.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_cond.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_idle.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_suspend.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_api.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_bus26m.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_cpu_buck_ldo.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_dram.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_syspll.c
+LOCAL_SRCS-${MT_SPM_SSPM_NOTIFIER_SUPPORT} += ${UPPER_DIR}/version/notifier/v1/mt_spm_sspm_notifier.c
+
+ifeq (${MT_SPM_FEATURE_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_CIRQ_UNSUPPORT))
+endif
+
+ifeq (${MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_UART_SUSPEND_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_UART_UNSUPPORT))
+endif
+
+ifeq ($(MTK_VOLTAGE_BIN_VCORE),y)
+$(eval $(call add_define,MTK_VOLTAGE_BIN_VCORE_SUPPORT))
+endif
+
+ifeq ($(MT_SPM_RGU_SUPPORT),n)
+$(eval $(call add_define,MTK_PLAT_SPM_RGU_UNSUPPORT))
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

plat/mediatek/drivers/spm/mt8188/sleep_def.h

@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SLEEP_DEF_H
+#define SLEEP_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN              (1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN            (1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN           (1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS            (1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS            (1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO      (1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF          (1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF           (1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH         (1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND       (1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO          (1U << 10)
+#define SPM_FLAG_PERI_ON_IN_SUSPEND           (1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP      (1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2               (1U << 13)
+#define SPM_FLAG_ENABLE_6315_CTRL             (1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND        (1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP         (1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP      (1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP     (1U << 18)
+#define SPM_FLAG_DISABLE_DRAMC_ISSUE_CMD      (1U << 19)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN           (1U << 20)
+#define SPM_FLAG_RESERVED_BIT21               (1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
+#define SPM_FLAG_DISABLE_DRAMC_MD32_BACKUP    (1U << 23)
+#define SPM_FLAG_RESERVED_BIT24               (1U << 24)
+#define SPM_FLAG_RESERVED_BIT25               (1U << 25)
+#define SPM_FLAG_RESERVED_BIT26               (1U << 26)
+#define SPM_FLAG_VTCXO_STATE                  (1U << 27)
+#define SPM_FLAG_INFRA_STATE                  (1U << 28)
+#define SPM_FLAG_APSRC_STATE                  (1U << 29)
+#define SPM_FLAG_VRF18_STATE                  (1U << 30)
+#define SPM_FLAG_DDREN_STATE                  (1U << 31)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M      (1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF          (1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH    (1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF          (1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON            (1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5               (1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK               (1U << 6)
+#define SPM_FLAG1_RESERVED_BIT7               (1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8               (1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9               (1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW         (1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH      (1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12              (1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13              (1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14              (1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15              (1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16              (1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17              (1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18              (1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19              (1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP   (1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21              (1U << 21)
+#define SPM_FLAG1_ENABLE_VS1_VOTER            (1U << 22)
+#define SPM_FLAG1_ENABLE_VS2_VOTER            (1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL   (1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25              (1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26              (1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27              (1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28              (1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29              (1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30              (1U << 30)
+#define SPM_FLAG1_RESERVED_BIT31              (1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE            (1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP           (1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE          (1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP         (1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE          (1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP         (1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE          (1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP         (1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE          (1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP         (1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC    (1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE    (1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE     (1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN    (1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE   (1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP          (1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON           (1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP      (1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON       (1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP       (1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON        (1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP    (1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON    (1U << 22)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V    (1U << 23)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V    (1U << 24)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V    (1U << 25)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V    (1U << 26)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW   (1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE         (1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE         (1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE         (1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE         (1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP      (1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START   (1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF         (1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON          (1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS   (1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF   (1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON    (1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT   (1U << 7)
+#define SPM_DBG1_RESERVED_BIT8                (1U << 8)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF   (1U << 9)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON   (1U << 10)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC   (1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M   (1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K     (1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M     (1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF        (1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON         (1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW       (1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH      (1U << 18)
+#define SPM_DBG1_RESERVED_BIT19               (1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON   (1U << 20)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW		(1U << 21)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH		(1U << 22)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT   (1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT   (1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT   (1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT   (1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT   (1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT   (1U << 28)
+#define SPM_DBG1_RESERVED_BIT29               (1U << 29)
+#define SPM_DBG1_RESERVED_BIT30               (1U << 30)
+#define SPM_DBG1_RESERVED_BIT31               (1U << 31)
+
+/*
+ * Macro and Inline
+ */
+#define is_cpu_pdn(flags)		((flags) & SPM_FLAG_DIS_CPU_PDN == 0)
+#define is_infra_pdn(flags)		((flags) & SPM_FLAG_DIS_INFRA_PDN == 0)
+#define is_ddrphy_pdn(flags)		((flags) & SPM_FLAG_DIS_DDRPHY_PDN == 0)
+
+#endif /* SLEEP_DEF_H */

plat/mediatek/drivers/spm/rules.mk

@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+MODULE := spm
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
+
+ifneq ($(CONFIG_MTK_SPM_VERSION),)
+PLAT_INCLUDES += -I${LOCAL_DIR}/$(MTK_SOC)
+PLAT_INCLUDES += -I${LOCAL_DIR}/version/notifier/inc
+
+SUB_RULES-y += ${LOCAL_DIR}/$(CONFIG_MTK_SPM_VERSION)
+$(eval $(call add_define,SPM_PLAT_IMPL))
+endif
+
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))

plat/mediatek/drivers/spm/version/notifier/inc/mt_spm_notifier.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_NOTIFIER_H
+#define MT_SPM_NOTIFIER_H
+
+enum mt_spm_sspm_notify_id {
+	MT_SPM_NOTIFY_LP_ENTER = 0,
+	MT_SPM_NOTIFY_LP_LEAVE,
+	MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE,
+};
+
+#ifdef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+static inline int mt_spm_sspm_notify_u32(int type, unsigned int val)
+{
+	(void)type;
+	(void)val;
+	return 0;
+}
+#else
+int mt_spm_sspm_notify_u32(int type, unsigned int val);
+#endif
+
+#endif /* MT_SPM_NOTIFIER_H */

plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_intc.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_INTC_H
+#define MT_SPM_SSPM_INTC_H
+
+#include <mt_spm_reg.h>
+
+#define MT_SPM_SSPM_INTC_SEL_0	(0x10)
+#define MT_SPM_SSPM_INTC_SEL_1	(0x20)
+#define MT_SPM_SSPM_INTC_SEL_2	(0x40)
+#define MT_SPM_SSPM_INTC_SEL_3	(0x80)
+
+#define MT_SPM_SSPM_INTC_TRIGGER(id, sg)	(((0x10 << (id)) | (sg << (id))) & 0xFF)
+
+#define MT_SPM_SSPM_INTC0_HIGH	MT_SPM_SSPM_INTC_TRIGGER(0, 1)
+#define MT_SPM_SSPM_INTC0_LOW	MT_SPM_SSPM_INTC_TRIGGER(0, 0)
+
+#define MT_SPM_SSPM_INTC1_HIGH	MT_SPM_SSPM_INTC_TRIGGER(1, 1)
+#define MT_SPM_SSPM_INTC1_LOW	MT_SPM_SSPM_INTC_TRIGGER(1, 0)
+
+#define MT_SPM_SSPM_INTC2_HIGH	MT_SPM_SSPM_INTC_TRIGGER(2, 1)
+#define MT_SPM_SSPM_INTC2_LOW	MT_SPM_SSPM_INTC_TRIGGER(2, 0)
+
+#define MT_SPM_SSPM_INTC3_HIGH	MT_SPM_SSPM_INTC_TRIGGER(3, 1)
+#define MT_SPM_SSPM_INTC3_LOW	MT_SPM_SSPM_INTC_TRIGGER(3, 0)
+
+#define DO_SPM_SSPM_LP_SUSPEND()	mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
+
+#define DO_SPM_SSPM_LP_RESUME()		mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
+
+#endif /* MT_SPM_SSPM_INTC_H */

plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_notifier.c

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include "mt_spm_notifier.h"
+#include "mt_spm_sspm_intc.h"
+#include <platform_def.h>
+
+#define MT_SPM_SSPM_MBOX_OFF(x)	(SSPM_MBOX_3_BASE + x)
+#define MT_SPM_MBOX(slot)	MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
+
+/* LOOKUP SSPM_MBOX_SPM_LP1 */
+#define SSPM_MBOX_SPM_LP_LOOKUP1	MT_SPM_MBOX(0)
+/* LOOKUP SSPM_MBOX_SPM_LP2 */
+#define SSPM_MBOX_SPM_LP_LOOKUP2	MT_SPM_MBOX(1)
+
+#define SSPM_MBOX_SPM_LP1		MT_SPM_MBOX(2)
+#define SSPM_MBOX_SPM_LP2		MT_SPM_MBOX(3)
+
+int mt_spm_sspm_notify_u32(int type, unsigned int val)
+{
+	switch (type) {
+	case MT_SPM_NOTIFY_LP_ENTER:
+		mmio_write_32(SSPM_MBOX_SPM_LP1, val);
+		DO_SPM_SSPM_LP_SUSPEND();
+		break;
+	case MT_SPM_NOTIFY_LP_LEAVE:
+		mmio_write_32(SSPM_MBOX_SPM_LP1, val);
+		DO_SPM_SSPM_LP_RESUME();
+		break;
+	default:
+		panic();
+		break;
+	}
+	return 0;
+}

plat/mediatek/drivers/usb/mt8188/mt_usb.c

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <lpm/mt_lp_api.h>
+#include <platform_def.h>
+
+int mt_usb_init(void)
+{
+	INFO("[%s] mt_usb initialization\n", __func__);
+
+	/* Keep infra and peri on to support wake-up from USB */
+	mtk_usb_update(LPM_USB_ENTER);
+
+	return 0;
+}
+MTK_PLAT_SETUP_0_INIT(mt_usb_init);

plat/mediatek/drivers/usb/rules.mk

@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := usb
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/$(MTK_SOC)/mt_usb.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

plat/mediatek/include/drivers/spm/mt_spm_resource_req.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM	(0U)
+#define MT_SPM_BIT_26M		(1U)
+#define MT_SPM_BIT_INFRA	(2U)
+#define MT_SPM_BIT_SYSPLL	(3U)
+#define MT_SPM_BIT_DRAM_S0	(4U)
+#define MT_SPM_BIT_DRAM_S1	(5U)
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM	BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M	BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA	BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL	BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0	BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1	BIT(MT_SPM_BIT_DRAM_S1)
+
+#endif /* MT_SPM_RESOURCE_REQ_H */

plat/mediatek/include/lpm/mt_lp_api.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_API_H
+#define MT_LP_API_H
+
+#include <lpm/mt_lp_rm.h>
+
+#if MTK_PUBEVENT_ENABLE
+#include <vendor_pubsub_events.h>
+#endif
+
+/* Ufs clk enum for PLAT_RC_CLKBUF_STATUS */
+enum rc_update_ex_ufs_ref_clk {
+	UFS_REF_CLK_OFF = 0,
+	UFS_REF_CLK_ON,
+};
+
+/* Enum for flight mode  */
+enum rc_update_ex_flight_mode {
+	FLIGHT_MODE_OFF = 0,
+	FLIGHT_MODE_ON,
+};
+
+struct mt_lpm_pubevent_data {
+	unsigned int u32;
+};
+
+enum mt_lpm_pubevents_id {
+	MT_LPM_PUBEVENTS_BBLPM_ENTER,
+	MT_LPM_PUBEVENTS_BBLPM_LEAVE,
+	MT_LPM_PUBEVENTS_TARGET_CORE,
+	MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+	MT_LPM_PUBEVENTS_SYS_POWER_ON,
+};
+
+struct mt_lp_publish_event {
+	unsigned int id;
+	struct mt_lpm_pubevent_data val;
+};
+
+#if MTK_PUBEVENT_ENABLE
+#define MT_LP_PUBLISH_EVENT(x) ({\
+	PUBLISH_EVENT_ARG(lpm_publish_event, (const void *)(x)); })
+#define MT_LP_SUSPEND_PUBLISH_EVENT(x) ({\
+	PUBLISH_EVENT_ARG(suspend_publish_event, (const void *)(x)); })
+
+#define MT_LP_SUBSCRIBE_SUSPEND(func)	SUBSCRIBE_TO_EVENT(suspend_publish_event, func)
+#define MT_LP_SUBSCRIBE_LPM(func)	SUBSCRIBE_TO_EVENT(lpm_publish_event, func)
+#else
+#define MT_LP_PUBLISH_EVENT(x) ({ (void)x; })
+#define MT_LP_SUSPEND_PUBLISH_EVENT(x) ({ (void)x; })
+#define MT_LP_SUBSCRIBE_SUSPEND(func)
+#define MT_LP_SUBSCRIBE_LPM(func)
+#endif
+
+/* MTK low power API types for audio */
+enum mt_lp_api_audio_type {
+	AUDIO_AFE_ENTER,
+	AUDIO_AFE_LEAVE,
+	AUDIO_DSP_ENTER,
+	AUDIO_DSP_LEAVE,
+};
+
+/* MTK low power API types for usb */
+enum mt_lp_api_usb_type {
+	LPM_USB_ENTER,
+	LPM_USB_LEAVE,
+};
+
+int mt_audio_update(int type);
+int mtk_usb_update(int type);
+
+#endif /* MT_LP_API_H */

plat/mediatek/include/lpm/mt_lp_rm.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RM_H
+#define MT_LP_RM_H
+
+#include <stdbool.h>
+
+#define MT_RM_STATUS_OK		(0)
+#define MT_RM_STATUS_BAD	(-1)
+#define MT_RM_STATUS_STOP	(-2)
+
+enum PLAT_MT_LPM_RC_TYPE {
+	PLAT_RC_UPDATE_CONDITION,
+	PLAT_RC_STATUS,
+	PLAT_RC_UPDATE_REMAIN_IRQS,
+	PLAT_RC_IS_FMAUDIO,
+	PLAT_RC_IS_ADSP,
+	PLAT_RC_ENTER_CNT,
+	PLAT_RC_CLKBUF_STATUS,
+	PLAT_RC_UFS_STATUS,
+	PLAT_RC_IS_USB_PERI,
+	PLAT_RC_IS_USB_INFRA,
+	PLAT_RC_MAX,
+};
+
+enum plat_mt_lpm_hw_ctrl_type {
+	PLAT_AP_MDSRC_REQ,
+	PLAT_AP_MDSRC_ACK,
+	PLAT_AP_IS_MD_SLEEP,
+	PLAT_AP_MDSRC_SETTLE,
+	PLAT_AP_GPUEB_PLL_CONTROL,
+	PLAT_AP_GPUEB_GET_PWR_STATUS,
+	PLAT_AP_HW_CTRL_MAX,
+};
+
+struct mt_resource_constraint {
+	int level;
+	int (*init)(void);
+	bool (*is_valid)(unsigned int cpu, int stateid);
+	int (*update)(int stateid, int type, const void *p);
+	int (*run)(unsigned int cpu, int stateid);
+	int (*reset)(unsigned int cpu, int stateid);
+	int (*get_status)(unsigned int type, void *priv);
+	unsigned int (*allow)(int stateid);
+};
+
+struct mt_resource_manager {
+	int (*update)(struct mt_resource_constraint **con, unsigned int num,
+		      int stateid, void *priv);
+	struct mt_resource_constraint **consts;
+};
+
+extern int mt_lp_rm_register(struct mt_resource_manager *rm);
+extern int mt_lp_rm_do_constraint(unsigned int constraint_id, unsigned int cpuid, int stateid);
+extern int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid,
+				    int stateid, void *priv);
+extern int mt_lp_rm_find_and_run_constraint(unsigned int idx, unsigned int cpuid,
+					    int stateid, void *priv);
+extern int mt_lp_rm_reset_constraint(unsigned int idx, unsigned int cpuid, int stateid);
+extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
+extern int mt_lp_rm_get_status(unsigned int type, void *priv);
+
+#endif /* MT_LP_RM_H */

plat/mediatek/include/lpm/mt_lp_rq.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RQ_H
+#define MT_LP_RQ_H
+
+/* Determine the generic resource request public type */
+#define MT_LP_RQ_XO_FPM		BIT(0)
+#define MT_LP_RQ_26M		BIT(1)
+#define MT_LP_RQ_INFRA		BIT(2)
+#define MT_LP_RQ_SYSPLL		BIT(3)
+#define MT_LP_RQ_DRAM		BIT(4)
+#define MT_LP_RQ_ALL		(0xFFFFFFFF)
+
+struct mt_lp_resource_user {
+	/* Determine the resource user mask */
+	unsigned int umask;
+	/* Determine the resource request user identify */
+	unsigned int uid;
+	/* Request the resource */
+	int (*request)(struct mt_lp_resource_user *this, unsigned int resource);
+	/* Release the resource */
+	int (*release)(struct mt_lp_resource_user *this);
+};
+
+int mt_lp_resource_user_register(char *uname, struct mt_lp_resource_user *ru);
+
+#endif /* MT_LP_RQ_H */

plat/mediatek/include/lpm/mt_lp_rqm.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RQM_H
+#define MT_LP_RQM_H
+
+#include "mt_lp_rq.h"
+
+enum plat_mt_lpm_rq_update_type {
+	PLAT_RQ_USER_NUM,
+	PLAT_RQ_USER_VALID,
+	PLAT_RQ_USER_REQ,
+	PLAT_RQ_USER_REL,
+	PLAT_RQ_PER_USER_NAME,
+	PLAT_RQ_REQ_NUM,
+	PLAT_RQ_REQ_USAGE,
+};
+
+/* Determine the request valid */
+#define MT_LP_RQ_VALID		(0x1)
+#define MT_LP_RQ_INVALID	(0x0)
+
+/* Determine the request user opertions */
+#define MT_LP_RQ_USER_INVALID	(-1)
+#define MT_LP_RQ_USER_MAX	(32)
+#define MT_LP_RQ_USER_NAME_LEN	(4)
+#define MT_LP_RQ_USER_CHAR_U	(8)
+
+/* Determine the request update flag */
+#define MT_LP_RQ_FLAG_DONE		(0)
+#define MT_LP_RQ_FLAG_NEED_UPDATE	BIT(6)
+
+/* Determine the resource update id */
+#define MT_LP_RQ_ID_ALL_USAGE	(-1)
+
+/* Determine the return status */
+#define MT_LP_RQ_STA_OK		(0)
+#define MT_LP_RQ_STA_BAD	(-1)
+
+struct mt_lp_res_req {
+	/* Determine the resource req public identify */
+	const unsigned int res_id;
+	/* Determine the resource bitwise internal control */
+	const unsigned int res_rq;
+	/* Determine the users per bit for current resource usage */
+	unsigned int res_usage;
+};
+
+struct mt_resource_req_manager {
+	/* Determine the set of resources */
+	struct mt_lp_res_req **res;
+};
+
+struct resource_req_status {
+	/* Determine the status id */
+	unsigned int id;
+	/* Determine the status value */
+	unsigned int val;
+};
+
+int mt_lp_resource_request_manager_register(struct mt_resource_req_manager *rqm);
+int mt_lp_rq_update_status(int type, void *p);
+int mt_lp_rq_get_status(int type, void *p);
+
+#endif /* MT_LP_RQM_H */

plat/mediatek/include/lpm/mt_lpm_smc.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LPM_SMC_H
+#define MT_LPM_SMC_H
+
+/*
+ * MTK LPM smc user format:
+ * bit[31:24]: magic number
+ * bit[23:16]: user number
+ * bit[15:00]: user id
+ */
+
+#define MT_LPM_SMC_MAGIC	(0xDA000000)
+#define MT_LPM_SMC_MAGIC_MASK	(0xFF000000)
+#define MT_LPM_SMC_USER_MASK	(0xFF)
+#define MT_LPM_SMC_USER_SHIFT	(16)
+
+#define MT_LPM_SMC_USER_ID_MASK	(0x0000FFFF)
+
+/*
+ * cpu_pm is used for MCDI to read/write CPC information
+ * spm_dbg is used for spm related debug information
+ * spm is used for spm related settings
+ * cpu_pm_lp is used for MCDI setting irq_remain
+ */
+enum mt_lpm_smc_user_id {
+	MT_LPM_SMC_USER_CPU_PM = 0,
+	MT_LPM_SMC_USER_SPM_DBG,
+	MT_LPM_SMC_USER_SPM,
+	MT_LPM_SMC_USER_CPU_PM_LP,
+	MT_LPM_SMC_USER_SECURE_CPU_PM,
+	MT_LPM_SMC_USER_SECURE_SPM_DBG,
+	MT_LPM_SMC_USER_SECURE_SPM,
+	MT_LPM_SMC_USER_MAX,
+};
+
+#define IS_MT_LPM_SMC(smcid)	((smcid & MT_LPM_SMC_MAGIC_MASK) == MT_LPM_SMC_MAGIC)
+
+/* get real user id */
+#define MT_LPM_SMC_USER(id)	((id >> MT_LPM_SMC_USER_SHIFT) & MT_LPM_SMC_USER_MASK)
+#define MT_LPM_SMC_USER_ID(uid)	(uid & MT_LPM_SMC_USER_ID_MASK)
+
+/* sink user id to smc's user id */
+#define MT_LPM_SMC_USER_SINK(user, uid)	(((uid & MT_LPM_SMC_USER_ID_MASK) |\
+					((user & MT_LPM_SMC_USER_MASK) << MT_LPM_SMC_USER_SHIFT)) |\
+					MT_LPM_SMC_MAGIC)
+
+/* sink cpu pm's smc id */
+#define MT_LPM_SMC_USER_ID_CPU_PM(uid)	MT_LPM_SMC_USER_SINK(MT_LPM_SMC_USER_CPU_PM, uid)
+/* sink spm's smc id */
+#define MT_LPM_SMC_USER_ID_SPM(uid)	MT_LPM_SMC_USER_SINK(MT_LPM_SMC_USER_SPM, uid)
+
+/* sink cpu pm's user id */
+#define MT_LPM_SMC_USER_CPU_PM(uid)	MT_LPM_SMC_USER_ID_CPU_PM(uid)
+
+/* sink spm's user id */
+#define MT_LPM_SMC_USER_SPM(uid)	MT_LPM_SMC_USER_ID_SPM(uid)
+
+/* behavior */
+#define MT_LPM_SMC_ACT_SET		BIT(0)
+#define MT_LPM_SMC_ACT_CLR		BIT(1)
+#define MT_LPM_SMC_ACT_GET		BIT(2)
+#define MT_LPM_SMC_ACT_PUSH		BIT(3)
+#define MT_LPM_SMC_ACT_POP		BIT(4)
+#define MT_LPM_SMC_ACT_SUBMIT		BIT(5)
+
+/* compatible action for legacy smc from lk */
+#define MT_LPM_SMC_ACT_COMPAT		BIT(31)
+
+enum mt_lpm_spmc_compat_id {
+	MT_LPM_SPMC_COMPAT_LK_FW_INIT,
+	MT_LPM_SPMC_COMPAT_LK_MCDI_WDT_DUMP,
+};
+
+#endif /* MT_LPM_SMC_H */

plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -148,7 +148,8 @@ unsigned int mt_spm_cond_check(int state_id,
 	(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) &&	\
 	 ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
 
-int mt_spm_cond_update(struct mt_resource_constraint **con, int stateid, void *priv)
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+		       int stateid, void *priv)
 {
 	int res;
 	uint32_t i;

plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -54,7 +54,7 @@ extern unsigned int mt_spm_cond_check(int state_id,
 				      const struct mt_spm_cond_tables *dest,
 				      struct mt_spm_cond_tables *res);
 
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
 			      int stateid, void *priv);
 
 #endif /* MT_SPM_CONDIT_H */

plat/mediatek/mt8186/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,7 +8,6 @@ MTK_PLAT     := plat/mediatek
 MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
-                 -I${MTK_PLAT}/common/lpm                         \
                  -I${MTK_PLAT}/drivers/cirq/                      \
                  -I${MTK_PLAT}/drivers/gic600/                    \
                  -I${MTK_PLAT}/drivers/gpio/                      \
@@ -18,6 +17,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT}/drivers/timer/                     \
                  -I${MTK_PLAT}/drivers/uart/                      \
                  -I${MTK_PLAT}/include/                           \
+                 -I${MTK_PLAT}/include/lpm                        \
                  -I${MTK_PLAT_SOC}/drivers/spm/                   \
                  -I${MTK_PLAT_SOC}/drivers/dcm/                   \
                  -I${MTK_PLAT_SOC}/drivers/dfd/                   \

plat/mediatek/mt8188/include/platform_def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,6 +22,8 @@
 #define MTK_DEV_RNG1_BASE	(IO_PHYS)
 #define MTK_DEV_RNG1_SIZE	(0x10000000)
 
+#define TOPCKGEN_BASE		(IO_PHYS)
+
 /*******************************************************************************
  * AUDIO related constants
  ******************************************************************************/
@@ -57,6 +59,8 @@
 /*******************************************************************************
  * Infra IOMMU related constants
  ******************************************************************************/
+#define INFRACFG_AO_BASE	(IO_PHYS + 0x00001000)
+#define INFRACFG_AO_MEM_BASE	(IO_PHYS + 0x00002000)
 #define PERICFG_AO_BASE		(IO_PHYS + 0x01003000)
 #define PERICFG_AO_REG_SIZE	(0x1000)
 
@@ -107,6 +111,33 @@
 #define SMI_LARB_28_BASE	(IO_PHYS + 0x00000000)
 #define SMI_LARB_REG_RNG_SIZE	(0x1000)
 
+/*******************************************************************************
+ * SPM related constants
+ ******************************************************************************/
+#define SPM_BASE		(IO_PHYS + 0x00006000)
+
+/*******************************************************************************
+ * APMIXEDSYS related constants
+ ******************************************************************************/
+#define APMIXEDSYS		(IO_PHYS + 0x0000C000)
+
+/*******************************************************************************
+ * VPPSYS related constants
+ ******************************************************************************/
+#define VPPSYS0_BASE		(IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE		(IO_PHYS + 0x04f00000)
+
+/*******************************************************************************
+ * VDOSYS related constants
+ ******************************************************************************/
+#define VDOSYS0_BASE		(IO_PHYS + 0x0C01D000)
+#define VDOSYS1_BASE		(IO_PHYS + 0x0C100000)
+
+/*******************************************************************************
+ * SSPM_MBOX_3 related constants
+ ******************************************************************************/
+#define SSPM_MBOX_3_BASE	(IO_PHYS + 0x00480000)
+
 /*******************************************************************************
  * DP related constants
  ******************************************************************************/

plat/mediatek/mt8188/plat_config.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -41,6 +41,8 @@ CONFIG_MTK_CPU_PM_SUPPORT := y
 CONFIG_MTK_CPU_PM_ARCH := 3_2
 CONFIG_MTK_SMP_EN := y
 CONFIG_MTK_CPU_SUSPEND_EN := y
+CONFIG_MTK_SPM_VERSION := mt8188
+CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y
 CPU_PM_TINYSYS_SUPPORT := y
 MTK_PUBEVENT_ENABLE := y
 

plat/mediatek/mt8188/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -39,7 +39,9 @@ MODULES-y += $(MTK_PLAT)/drivers/pmic
 MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
 MODULES-y += $(MTK_PLAT)/drivers/ptp3
 MODULES-y += $(MTK_PLAT)/drivers/rtc
+MODULES-y += $(MTK_PLAT)/drivers/spm
 MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-y += $(MTK_PLAT)/drivers/usb
 MODULES-y += $(MTK_PLAT)/helpers
 MODULES-y += $(MTK_PLAT)/topology
 

plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -155,7 +155,7 @@ unsigned int mt_spm_cond_check(int state_id,
 	(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) &&	\
 	 ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
 
-int mt_spm_cond_update(struct mt_resource_constraint **con,
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
 		       int stateid, void *priv)
 {
 	int res;

plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -51,6 +51,6 @@ extern unsigned int mt_spm_cond_check(int state_id,
 				      const struct mt_spm_cond_tables *src,
 				      const struct mt_spm_cond_tables *dest,
 				      struct mt_spm_cond_tables *res);
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
 			      int stateid, void *priv);
 #endif /* MT_SPM_CONDIT_H */

plat/mediatek/mt8192/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,7 +8,6 @@ MTK_PLAT      := plat/mediatek
 MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
-                 -I${MTK_PLAT}/common/lpm/                        \
                  -I${MTK_PLAT}/drivers/cirq/                      \
                  -I${MTK_PLAT}/drivers/gic600/                    \
                  -I${MTK_PLAT}/drivers/gpio/                      \
@@ -18,6 +17,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT}/drivers/timer/                     \
                  -I${MTK_PLAT}/drivers/uart/                      \
                  -I${MTK_PLAT}/include/                           \
+                 -I${MTK_PLAT}/include/lpm/                       \
                  -I${MTK_PLAT_SOC}/include/                       \
                  -I${MTK_PLAT_SOC}/drivers/                       \
                  -I${MTK_PLAT_SOC}/drivers/apusys/                \

plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -171,7 +171,7 @@ unsigned int mt_spm_cond_check(int state_id,
 	(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) &&	\
 	 ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
 
-int mt_spm_cond_update(struct mt_resource_constraint **con,
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
 		       int stateid, void *priv)
 {
 	int res;

plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -68,6 +68,6 @@ extern unsigned int mt_spm_cond_check(int state_id,
 				      const struct mt_spm_cond_tables *src,
 				      const struct mt_spm_cond_tables *dest,
 				      struct mt_spm_cond_tables *res);
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
 			      int stateid, void *priv);
 #endif /* MT_SPM_CONDIT_H */

plat/mediatek/mt8195/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,7 +8,6 @@ MTK_PLAT     := plat/mediatek
 MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
-                 -I${MTK_PLAT}/common/lpm/                        \
                  -I${MTK_PLAT}/drivers/cirq/                      \
                  -I${MTK_PLAT}/drivers/dp/                        \
                  -I${MTK_PLAT}/drivers/gic600/                    \
@@ -20,6 +19,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT}/drivers/timer/                     \
                  -I${MTK_PLAT}/drivers/uart/                      \
                  -I${MTK_PLAT}/include/                           \
+                 -I${MTK_PLAT}/include/lpm/                       \
                  -I${MTK_PLAT_SOC}/drivers/apusys/                \
                  -I${MTK_PLAT_SOC}/drivers/dcm                    \
                  -I${MTK_PLAT_SOC}/drivers/dfd                    \