From 7f7a16a6c0a49af593fa080eb66f72a20bb07299 Mon Sep 17 00:00:00 2001 From: Jit Loon Lim Date: Thu, 2 Mar 2023 13:38:53 +0800 Subject: [PATCH] fix(intel): update boot scratch to indicate to Uboot is PSCI ON There is a use case where kernel requested ATF to power off/on only CPU0. However, after ATF power off/on CPU0, CPU0 did not back into the state to wait for ATF. Instead, CPU0 continue to reentry SPL boot sequence because CPU0 is master/primary core. This causing the system reboot from SPL again, while the slave core still in kernel. To resolve this, ATF is set the boot scratch register 8 bit 17 whenever it is a request from kernel to power off/on only CPU0. So, if this boot scratch bit is set, CPU 0 will be able to put into a state to wait for ATF. Signed-off-by: Jit Loon Lim Change-Id: Ia0228c5396beaa479858f5bd02fc05139efd2423 --- plat/intel/soc/common/socfpga_psci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index 5fd6559f2..bdece935c 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -14,6 +14,7 @@ #include "socfpga_mailbox.h" #include "socfpga_plat_def.h" #include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" #include "socfpga_sip_svc.h" @@ -38,12 +39,19 @@ void socfpga_cpu_standby(plat_local_state_t cpu_state) int socfpga_pwr_domain_on(u_register_t mpidr) { unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); + uint32_t psci_boot = 0x00; VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); if (cpu_id == -1) return PSCI_E_INTERN_FAIL; + if (cpu_id == 0x00) { + psci_boot = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)); + psci_boot |= 0x20000; /* bit 17 */ + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8), psci_boot); + } + mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); /* release core reset */