Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs

A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers. T210 is the
only platform that needs to enable this config for now.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/nvidia/tegra/common/aarch64/tegra_helpers.S

@@ -57,6 +57,7 @@
 	 */
 .macro	cpu_init_common
 
+#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
 	/* -------------------------------------------------------
 	 * Enable L2 and CPU ECTLR RW access from non-secure world
 	 * -------------------------------------------------------
@@ -65,6 +66,7 @@
 	msr	actlr_el3, x0
 	msr	actlr_el2, x0
 	isb
+#endif
 
 	/* --------------------------------
 	 * Enable the cycle count register

plat/nvidia/tegra/soc/t210/platform_t210.mk

@@ -37,6 +37,9 @@ $(eval $(call add_define,TZDRAM_BASE))
 ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT	:= 1
 $(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
 
+ENABLE_NS_L2_CPUECTRL_RW_ACCESS		:= 1
+$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
+
 PLATFORM_CLUSTER_COUNT			:= 2
 $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
 
@@ -49,3 +52,4 @@ BL31_SOURCES		+=	${SOC_DIR}/plat_psci_handlers.c \
 
 # Enable workarounds for selected Cortex-A53 erratas.
 ERRATA_A53_826319	:=	1
+