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PSCI: Migrate TF to the new platform API and CM helpers 

This patch migrates the rest of Trusted Firmware excluding Secure Payload and
the dispatchers to the new platform and context management API. The per-cpu
data framework APIs which took MPIDRs as their arguments are deleted and only
the ones which take core index as parameter are retained.

Change-Id: I839d05ad995df34d2163a1cfed6baa768a5a595d
pull/361/head
Soby Mathew 9 years ago
committed by Achin Gupta
parent
5c8babcd70
commit
85a181ce38
7 changed files with 17 additions and 43 deletions
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  1. 5
      bl2/aarch64/bl2_entrypoint.S
  2. 31
      bl31/aarch64/cpu_data.S
  3. 4
      bl31/bl31_main.c
  4. 5
      include/bl31/cpu_data.h
  5. 9
      include/common/el3_common_macros.S
  6. 4
      lib/locks/bakery/bakery_lock_coherent.c
  7. 2
      lib/locks/bakery/bakery_lock_normal.c

5
bl2/aarch64/bl2_entrypoint.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -105,8 +105,7 @@ func bl2_entrypoint
* primary cpu is running at the moment.
* --------------------------------------------
*/
mrs x0, mpidr_el1
bl platform_set_stack
bl plat_set_my_stack
/* ---------------------------------------------
* Perform early platform setup & platform

31
bl31/aarch64/cpu_data.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,7 +32,6 @@
#include <cpu_data.h>
.globl init_cpu_data_ptr
.globl _cpu_data_by_mpidr
.globl _cpu_data_by_index
/* -----------------------------------------------------------------
@ -41,37 +40,19 @@
* Initialise the TPIDR_EL3 register to refer to the cpu_data_t
* for the calling CPU. This must be called before cm_get_cpu_data()
*
* This can be called without a valid stack.
* clobbers: x0, x1, x9, x10
* This can be called without a valid stack. It assumes that
* plat_my_core_pos() does not clobber register x10.
* clobbers: x0, x1, x10
* -----------------------------------------------------------------
*/
func init_cpu_data_ptr
mov x10, x30
mrs x0, mpidr_el1
bl _cpu_data_by_mpidr
bl plat_my_core_pos
bl _cpu_data_by_index
msr tpidr_el3, x0
ret x10
endfunc init_cpu_data_ptr
/* -----------------------------------------------------------------
* cpu_data_t *_cpu_data_by_mpidr(uint64_t mpidr)
*
* Return the cpu_data structure for the CPU with given MPIDR
*
* This can be called without a valid stack. It assumes that
* platform_get_core_pos() does not clobber register x9.
* clobbers: x0, x1, x9
* -----------------------------------------------------------------
*/
func _cpu_data_by_mpidr
mov x9, x30
bl platform_get_core_pos
mov x30, x9
b _cpu_data_by_index
endfunc _cpu_data_by_mpidr
/* -----------------------------------------------------------------
* cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
*

4
bl31/bl31_main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -155,7 +155,7 @@ void bl31_prepare_next_image_entry(void)
INFO("BL3-1: Next image address = 0x%llx\n",
(unsigned long long) next_image_info->pc);
INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr);
cm_init_context(read_mpidr_el1(), next_image_info);
cm_init_my_context(next_image_info);
cm_prepare_el3_exit(image_type);
}

5
include/bl31/cpu_data.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
assert_cpu_data_cpu_ops_ptr_offset_mismatch);
struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
struct cpu_data *_cpu_data_by_mpidr(uint64_t mpidr);
/* Return the cpu_data structure for the current CPU. */
static inline struct cpu_data *_cpu_data(void)
@ -123,8 +122,6 @@ void init_cpu_ops(void);
#define set_cpu_data(_m, _v) _cpu_data()->_m = _v
#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v
#define get_cpu_data_by_mpidr(_id, _m) _cpu_data_by_mpidr(_id)->_m
#define set_cpu_data_by_mpidr(_id, _m, _v) _cpu_data_by_mpidr(_id)->_m = _v
#define flush_cpu_data(_m) flush_dcache_range((uint64_t) \
&(_cpu_data()->_m), \

9
include/common/el3_common_macros.S
View File

@ -164,8 +164,7 @@
* then it means it is a warm boot so jump to this address.
* -------------------------------------------------------------
*/
mrs x0, mpidr_el1
bl platform_get_entrypoint
bl plat_get_my_entrypoint
cbz x0, do_cold_boot
br x0
@ -181,8 +180,7 @@
* of that state and allows entry into the OS.
* -------------------------------------------------------------
*/
mrs x0, mpidr_el1
bl platform_is_primary_cpu
bl plat_is_my_cpu_primary
cbnz x0, do_primary_cold_boot
/* This is a cold boot on a secondary CPU */
@ -249,8 +247,7 @@
* moment.
* ---------------------------------------------------------------------
*/
mrs x0, mpidr_el1
bl platform_set_stack
bl plat_set_my_stack
.endm
#endif /* __EL3_COMMON_MACROS_S__ */

4
lib/locks/bakery/bakery_lock_coherent.c
View File

@ -128,7 +128,7 @@ void bakery_lock_get(bakery_lock_t *bakery)
unsigned int my_ticket, my_prio, their_ticket;
unsigned int their_bakery_data;
me = platform_get_core_pos(read_mpidr_el1());
me = plat_my_core_pos();
assert_bakery_entry_valid(me, bakery);
@ -174,7 +174,7 @@ void bakery_lock_get(bakery_lock_t *bakery)
/* Release the lock and signal contenders */
void bakery_lock_release(bakery_lock_t *bakery)
{
unsigned int me = platform_get_core_pos(read_mpidr_el1());
unsigned int me = plat_my_core_pos();
assert_bakery_entry_valid(me, bakery);
assert(bakery_ticket_number(bakery->lock_data[me]));

2
lib/locks/bakery/bakery_lock_normal.c
View File

@ -148,7 +148,7 @@ void bakery_lock_get(unsigned int id, unsigned int offset)
bakery_info_t *their_bakery_info;
unsigned int their_bakery_data;
me = platform_get_core_pos(read_mpidr_el1());
me = plat_my_core_pos();
is_cached = read_sctlr_el3() & SCTLR_C_BIT;

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