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* changes: plat: marvell: armada: mcbin: squash several IO windows into one plat: marvell: armada: fix BL32 extra parameters usage drivers: marvell: Fix the LLC SRAM driver plat: marvell: armada: a8k: change CCU LLC SRAM mapping plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW plat: marvell: armada: move mg conf related code to appropriate driver marvell: comphy: start AP FW when comphy AP mode selected drivers: marvell: mg_conf_cm3: add basic driver tools: doimage: change the binary image alignment to 16 tools: doimage: migrate to mbedtls v2.8 APIspull/1979/head
Manish Pandey
4 years ago
committed by
TrustedFirmware Code Review
TrustedFirmware Code Review
20 changed files with 313 additions and 82 deletions
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/*
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* Copyright (C) 2019 Marvell International Ltd. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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* https://spdx.org/licenses
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*/ |
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#include <a8k_plat_def.h> |
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#include <arch_helpers.h> |
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#include <common/debug.h> |
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#include <lib/mmio.h> |
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#include <mss_scp_bl2_format.h> |
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/* CONFI REGISTERS */ |
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#define MG_CM3_CONFI_BASE(CP) (MVEBU_CP_REGS_BASE(CP) + 0x100000) |
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#define MG_CM3_SRAM_BASE(CP) MG_CM3_CONFI_BASE(CP) |
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#define MG_CM3_CONFI_GLOB_CFG_REG(CP) (MG_CM3_CONFI_BASE(CP) + 0x2B500) |
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#define CM3_CPU_EN_BIT BIT(28) |
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#define MG_CM3_MG_INT_MFX_REG(CP) (MG_CM3_CONFI_BASE(CP) + 0x2B054) |
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#define CM3_SYS_RESET_BIT BIT(0) |
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#define MG_CM3_SHARED_MEM_BASE(CP) (MG_CM3_SRAM_BASE(CP) + 0x1FC00ULL) |
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#define MG_SRAM_SIZE 0x20000 /* 128KB */ |
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#define MG_ACK_TIMEOUT 10 |
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/**
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* struct ap_sharedmem_ctrl - used to pass information between the HOST and CM3 |
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* @init_done: Set by CM3 when ap_proces initialzied. Host check if CM3 set |
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* this flag to confirm that the process is running |
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* @lane_nr: Set by Host to mark which comphy lane should be configure. E.g.: |
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* - A8K development board uses comphy lane 2 for eth0 |
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* - CN913x development board uses comphy lane 4 for eth0 |
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*/ |
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struct ap_sharedmem_ctrl { |
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uint32_t init_done; |
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uint32_t lane_nr; |
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}; |
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int mg_image_load(uintptr_t src_addr, uint32_t size, int cp_index) |
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{ |
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uintptr_t mg_regs = MG_CM3_SRAM_BASE(cp_index); |
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if (size > MG_SRAM_SIZE) { |
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ERROR("image is too big to fit into MG CM3 memory\n"); |
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return 1; |
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} |
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NOTICE("Loading MG image from address 0x%lx Size 0x%x to MG at 0x%lx\n", |
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src_addr, size, mg_regs); |
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/* Copy image to MG CM3 SRAM */ |
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memcpy((void *)mg_regs, (void *)src_addr, size); |
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/* Don't release MG CM3 from reset - it will be done by next step
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* bootloader (e.g. U-Boot), when appriopriate device-tree setup (which |
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* has enabeld 802.3. auto-neg) will be choosen. |
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*/ |
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return 0; |
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} |
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void mg_start_ap_fw(int cp_nr, uint8_t comphy_index) |
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{ |
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volatile struct ap_sharedmem_ctrl *ap_shared_ctrl = |
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(void *)MG_CM3_SHARED_MEM_BASE(cp_nr); |
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int timeout = MG_ACK_TIMEOUT; |
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if (mmio_read_32(MG_CM3_CONFI_GLOB_CFG_REG(cp_nr)) & CM3_CPU_EN_BIT) { |
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VERBOSE("cm3 already running\n"); |
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return; /* cm3 already running */ |
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} |
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/*
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* Mark which comphy lane should be used - it will be read via shared |
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* mem by ap process |
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*/ |
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ap_shared_ctrl->lane_nr = comphy_index; |
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/* Make sure it took place before enabling cm3 */ |
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dmbst(); |
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mmio_setbits_32(MG_CM3_CONFI_GLOB_CFG_REG(cp_nr), CM3_CPU_EN_BIT); |
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mmio_setbits_32(MG_CM3_MG_INT_MFX_REG(cp_nr), CM3_SYS_RESET_BIT); |
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/* Check for ap process initialization by fw */ |
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while (ap_shared_ctrl->init_done != 1 && timeout--) |
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VERBOSE("Waiting for ap process ack, timeout %d\n", timeout); |
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if (timeout == 0) { |
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ERROR("AP process failed, disabling cm3\n"); |
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mmio_clrbits_32(MG_CM3_MG_INT_MFX_REG(cp_nr), |
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CM3_SYS_RESET_BIT); |
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mmio_clrbits_32(MG_CM3_CONFI_GLOB_CFG_REG(cp_nr), |
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CM3_CPU_EN_BIT); |
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} |
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} |
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/*
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* Copyright (C) 2019 Marvell International Ltd. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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* https://spdx.org/licenses
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*/ |
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void mg_start_ap_fw(int cp_nr, uint8_t comphy_index); |
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int mg_image_load(uintptr_t src_addr, uint32_t size, int cp_index); |
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