Merge changes I1784d643,Icb6e3699,I7805756e into integration

* changes:
  fix(errata): workaround for Cortex-A510 erratum 2172148
  fix(errata): workaround for Cortex-A510 erratum 2218950
  fix(errata): workaround for Cortex-A510 erratum 2250311

docs/design/cpu-specific-build-macros.rst

@@ -493,6 +493,19 @@ For Cortex-A510, the following errata build flags are defined :
    in r0p3. The issue is also present in r0p0 and r0p1 but there is no
    workaround for those revisions.
 
+-  ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
+   ENABLE_MPMM=1.
+
+-  ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1.
+
+-  ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1.
+
 DSU Errata Workarounds
 ----------------------
 

include/lib/cpus/aarch64/cortex_a510.h

@@ -15,6 +15,8 @@
 #define CORTEX_A510_CPUECTLR_EL1				S3_0_C15_C1_4
 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT		U(19)
 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE	U(1)
+#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT			U(23)
+#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT			U(46)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions

lib/cpus/aarch64/cortex_a510.S

@@ -153,6 +153,117 @@ func check_errata_2041909
 	b	cpu_rev_var_range
 endfunc check_errata_2041909
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2250311.
+	 * This applies only to revisions r0p0, r0p1, r0p2,
+	 * r0p3 and r1p0, and is fixed in r1p1.
+	 * This workaround is not a typical errata fix. MPMM
+	 * is disabled here, but this conflicts with the BL31
+	 * MPMM support. So in addition to simply disabling
+	 * the feature, a flag is set in the MPMM library
+	 * indicating that it should not be enabled even if
+	 * ENABLE_MPMM=1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2250311_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2250311
+	cbz	x0, 1f
+
+	/* Disable MPMM */
+	mrs	x0, CPUMPMMCR_EL3
+	bfm	x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
+	msr	CPUMPMMCR_EL3, x0
+
+#if ENABLE_MPMM && IMAGE_BL31
+	/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
+	bl mpmm_errata_disable
+#endif
+
+1:
+	ret x17
+endfunc errata_cortex_a510_2250311_wa
+
+func check_errata_2250311
+	/* Applies to r1p0 and lower */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_2250311
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2218950.
+	 * This applies only to revisions r0p0, r0p1, r0p2,
+	 * r0p3 and r1p0, and is fixed in r1p1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2218950_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2218950
+	cbz	x0, 1f
+
+	/* Source register for BFI */
+	mov	x1, #1
+
+	/* Set bit 18 in CPUACTLR_EL1 */
+	mrs	x0, CORTEX_A510_CPUACTLR_EL1
+	bfi	x0, x1, #18, #1
+	msr	CORTEX_A510_CPUACTLR_EL1, x0
+
+	/* Set bit 25 in CMPXACTLR_EL1 */
+	mrs	x0, CORTEX_A510_CMPXACTLR_EL1
+	bfi	x0, x1, #25, #1
+	msr	CORTEX_A510_CMPXACTLR_EL1, x0
+
+1:
+	ret x17
+endfunc errata_cortex_a510_2218950_wa
+
+func check_errata_2218950
+	/* Applies to r1p0 and lower */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_2218950
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex-A510 Errata #2172148.
+	 * This applies only to revisions r0p0, r0p1, r0p2,
+	 * r0p3 and r1p0, and is fixed in r1p1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0, x1, x17
+	 * --------------------------------------------------
+	 */
+func errata_cortex_a510_2172148_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2172148
+	cbz	x0, 1f
+
+	/*
+	 * Force L2 allocation of transient lines by setting
+	 * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
+	 */
+	mrs	x0, CORTEX_A510_CPUECTLR_EL1
+	mov	x1, #1
+	bfi	x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
+	bfi	x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
+	msr	CORTEX_A510_CPUECTLR_EL1, x0
+
+1:
+	ret x17
+endfunc errata_cortex_a510_2172148_wa
+
+func check_errata_2172148
+	/* Applies to r1p0 and lower */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_2172148
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
@@ -187,6 +298,9 @@ func cortex_a510_errata_report
 	report_errata ERRATA_A510_2288014, cortex_a510, 2288014
 	report_errata ERRATA_A510_2042739, cortex_a510, 2042739
 	report_errata ERRATA_A510_2041909, cortex_a510, 2041909
+	report_errata ERRATA_A510_2250311, cortex_a510, 2250311
+	report_errata ERRATA_A510_2218950, cortex_a510, 2218950
+	report_errata ERRATA_A510_2172148, cortex_a510, 2172148
 
 	ldp	x8, x30, [sp], #16
 	ret
@@ -224,6 +338,21 @@ func cortex_a510_reset_func
 	bl	errata_cortex_a510_2041909_wa
 #endif
 
+#if ERRATA_A510_2250311
+	mov	x0, x18
+	bl	errata_cortex_a510_2250311_wa
+#endif
+
+#if ERRATA_A510_2218950
+	mov	x0, x18
+	bl	errata_cortex_a510_2218950_wa
+#endif
+
+#if ERRATA_A510_2172148
+	mov	x0, x18
+	bl	errata_cortex_a510_2172148_wa
+#endif
+
 	ret	x19
 endfunc cortex_a510_reset_func
 

lib/cpus/cpu-ops.mk

@@ -548,6 +548,18 @@ ERRATA_A510_2042739	?=0
 # present in r0p0 and r0p1 but there is no workaround for those revisions.
 ERRATA_A510_2041909	?=0
 
+# Flag to apply erratum 2250311 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
+ERRATA_A510_2250311	?=0
+
+# Flag to apply erratum 2218950 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
+ERRATA_A510_2218950	?=0
+
+# Flag to apply erratum 2172148 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
+ERRATA_A510_2172148	?=0
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 ERRATA_DSU_798953	?=0
@@ -1021,6 +1033,18 @@ $(eval $(call add_define,ERRATA_A510_2042739))
 $(eval $(call assert_boolean,ERRATA_A510_2041909))
 $(eval $(call add_define,ERRATA_A510_2041909))
 
+# Process ERRATA_A510_2250311 flag
+$(eval $(call assert_boolean,ERRATA_A510_2250311))
+$(eval $(call add_define,ERRATA_A510_2250311))
+
+# Process ERRATA_A510_2218950 flag
+$(eval $(call assert_boolean,ERRATA_A510_2218950))
+$(eval $(call add_define,ERRATA_A510_2218950))
+
+# Process ERRATA_A510_2172148 flag
+$(eval $(call assert_boolean,ERRATA_A510_2172148))
+$(eval $(call add_define,ERRATA_A510_2172148))
+
 # Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))

lib/mpmm/mpmm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -62,11 +62,25 @@ static bool mpmm_supported(void)
 	return supported;
 }
 
+/* Defaults to false */
+static bool mpmm_disable_for_errata;
+
 void mpmm_enable(void)
 {
-	bool supported = mpmm_supported();
-
-	if (supported) {
+	if (mpmm_supported()) {
+		if (mpmm_disable_for_errata) {
+			WARN("MPMM: disabled by errata workaround\n");
+			return;
+		}
 		write_cpumpmmcr_el3_mpmm_en(1U);
 	}
 }
+
+/*
+ * This function is called from assembly code very early in BL31 so it must be
+ * small and simple.
+ */
+void mpmm_errata_disable(void)
+{
+	mpmm_disable_for_errata = true;
+}