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Merge changes from topic "us_tc4_rebase_v2" into integration 

* changes:
  feat(tc): bind DPU SMMU on TC4
  feat(tc): bind GPU SMMU on TC4
  feat(tc): update DT for Drage GPU
  feat(tc): enable SME and SME2 options for TC4
  feat(tc): add new TC4 RoS definitions
  feat(tc): add system generic timer register definition for TC4
  feat(tc): allow TARGET_VERSION=4
  feat(tc): add MHUv3 register addresses for TC4
  feat(tc): add device tree binding for TC4
pull/2005/merge
Manish V Badarkhe 2 months ago
committed by TrustedFirmware Code Review
parent
241ec3a5af e365479d0d
commit
8e9bdc5b1d
11 changed files with 260 additions and 108 deletions
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  1. 23
      fdts/tc-base.dtsi
  2. 4
      fdts/tc-fpga.dtsi
  3. 22
      fdts/tc-fvp.dtsi
  4. 24
      fdts/tc2.dts
  5. 84
      fdts/tc3-4-base.dtsi
  6. 97
      fdts/tc3.dts
  7. 67
      fdts/tc4.dts
  8. 25
      plat/arm/board/tc/include/platform_def.h
  9. 4
      plat/arm/board/tc/include/tc_helpers.S
  10. 14
      plat/arm/board/tc/platform.mk
  11. 4
      plat/arm/board/tc/tc_bl31_setup.c

23
fdts/tc-base.dtsi
View File

@ -437,9 +437,9 @@
};
ethernet: ethernet@18000000 {
reg = <0x0 0x18000000 0x0 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
ethernet: ethernet@ETHERNET_ADDR {
reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>;
interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>;
reg-io-width = <2>;
smsc,irq-push-pull;
@ -452,10 +452,9 @@
clock-output-names = "bp:clock24mhz";
};
sysreg: sysreg@1c010000 {
sysreg: sysreg@SYS_REGS_ADDR {
compatible = "arm,vexpress-sysreg";
reg = <0x0 0x001c010000 0x0 0x1000>;
reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
@ -468,11 +467,11 @@
regulator-always-on;
};
mmci: mmci@1c050000 {
mmci: mmci@MMC_ADDR {
compatible = "arm,pl180", "arm,primecell";
reg = <0x0 0x001c050000 0x0 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>;
interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>;
wp-gpios = <&sysreg 1 0>;
bus-width = <4>;
max-frequency = <25000000>;
@ -496,10 +495,6 @@
gpu: gpu@2d000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x2d000000 0x0 0x200000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&gpu_core_clk>;
clock-names = "shadercores";
#if TC_SCMI_PD_CTRL_EN

4
fdts/tc-fpga.dtsi
View File

@ -25,12 +25,12 @@
stdout-path = "serial0:38400n8";
};
ethernet: ethernet@18000000 {
ethernet: ethernet@ETHERNET_ADDR {
compatible = "smsc,lan9115";
phy-mode = "mii";
};
mmci: mmci@1c050000 {
mmci: mmci@MMC_ADDR {
non-removable;
};
};

22
fdts/tc-fvp.dtsi
View File

@ -43,26 +43,26 @@
stdout-path = "serial0:115200n8";
};
ethernet: ethernet@18000000 {
ethernet: ethernet@ETHERNET_ADDR {
compatible = "smsc,lan91c111";
};
mmci: mmci@1c050000 {
mmci: mmci@MMC_ADDR {
cd-gpios = <&sysreg 0 0>;
};
rtc@1c170000 {
rtc@RTC_ADDR {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
reg = <0x0 ADDRESSIFY(RTC_ADDR) 0x0 0x1000>;
interrupts = <GIC_SPI RTC_INT IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
};
kmi@1c060000 {
kmi@KMI_0_ADDR {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c060000 0x0 0x1000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
reg = <0x0 ADDRESSIFY(KMI_0_ADDR) 0x0 0x1000>;
interrupts = <GIC_SPI KMI_0_INT IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
@ -75,10 +75,10 @@
clock-names = "KMIREFCLK", "apb_pclk";
};
virtio_block@1c130000 {
virtio_block@VIRTIO_BLOCK_ADDR {
compatible = "virtio,mmio";
reg = <0x0 0x1c130000 0x0 0x200>;
reg = <0x0 ADDRESSIFY(VIRTIO_BLOCK_ADDR) 0x0 0x200>;
/* spec lists this wrong */
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
interrupts = <GIC_SPI VIRTIO_BLOCK_INT IRQ_TYPE_LEVEL_HIGH 0>;
};
};

24
fdts/tc2.dts
View File

@ -41,6 +41,26 @@
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#define ETHERNET_ADDR 18000000
#define ETHERNET_INT 109
#define SYS_REGS_ADDR 1c010000
#define MMC_ADDR 1c050000
#define MMC_INT_0 107
#define MMC_INT_1 108
#define RTC_ADDR 1c170000
#define RTC_INT 100
#define KMI_0_ADDR 1c060000
#define KMI_0_INT 197
#define KMI_1_ADDR 1c070000
#define KMI_1_INT 103
#define VIRTIO_BLOCK_ADDR 1c130000
#define VIRTIO_BLOCK_INT 204
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
@ -271,6 +291,10 @@
};
gpu: gpu@2d000000 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
iommus = <&smmu_700 0x200>;
};
};

84
fdts/tc3-4-base.dtsi
View File

@ -0,0 +1,84 @@
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
#define MHU_TX_COMPAT "arm,mhuv3"
#define MHU_TX_INT_NAME ""
#define MHU_RX_COMPAT "arm,mhuv3"
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-base.dtsi"
/ {
cpus {
CPU2:cpu@200 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU3:cpu@300 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU6:cpu@600 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
CPU7:cpu@700 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
};
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>;
};
ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};
ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU6>, <&CPU7>;
};
};
};
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};
firmware {
scmi {
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};
};

97
fdts/tc3.dts
View File

@ -10,35 +10,32 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_TX_COMPAT "arm,mhuv3"
#define MHU_TX_INT_NAME ""
#define MHU_RX_ADDR 46140000 /* hex */
#define MHU_RX_COMPAT "arm,mhuv3"
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"
#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#define ETHERNET_ADDR 18000000
#define ETHERNET_INT 109
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#define SYS_REGS_ADDR 1c010000
#define MMC_ADDR 1c050000
#define MMC_INT_0 107
#define MMC_INT_1 108
#define RTC_ADDR 1c170000
#define RTC_INT 100
#define KMI_0_ADDR 1c060000
#define KMI_0_INT 197
#define KMI_1_ADDR 1c070000
#define KMI_1_INT 103
#define VIRTIO_BLOCK_ADDR 1c130000
#define VIRTIO_BLOCK_INT 204
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
@ -46,31 +43,9 @@
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc-base.dtsi"
#include "tc3-4-base.dtsi"
/ {
cpus {
CPU2:cpu@200 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU3:cpu@300 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU6:cpu@600 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
CPU7:cpu@700 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
};
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
@ -109,36 +84,6 @@
reg = <0x0 0x4f000000 0x0 0x4000000>;
};
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};
firmware {
scmi {
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>;
};
ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};
ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU6>, <&CPU7>;
};
};
};
#if TARGET_FLAVOUR_FVP
smmu_700: iommu@3f000000 {
status = "okay";
@ -165,6 +110,10 @@
};
gpu: gpu@2d000000 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
#if TARGET_FLAVOUR_FVP
iommus = <&smmu_700 0x200>;
#endif

67
fdts/tc4.dts
View File

@ -0,0 +1,67 @@
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>
#define MHU_TX_ADDR 46240000 /* hex */
#define MHU_RX_ADDR 46250000 /* hex */
#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define ETHERNET_ADDR 64000000
#define ETHERNET_INT 799
#define SYS_REGS_ADDR 60080000
#define MMC_ADDR 600b0000
#define MMC_INT_0 778
#define MMC_INT_1 779
#define RTC_ADDR 600a0000
#define RTC_INT 777
#define KMI_0_ADDR 60100000
#define KMI_0_INT 784
#define KMI_1_ADDR 60110000
#define KMI_1_INT 785
#define VIRTIO_BLOCK_ADDR 60020000
#define VIRTIO_BLOCK_INT 769
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc3-4-base.dtsi"
/ {
smmu_700: iommu@3f000000 {
status = "okay";
};
smmu_700_dpu: iommu@4002a00000 {
status = "okay";
};
dp0: display@DPU_ADDR {
iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
};
gpu: gpu@2d000000 {
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "IRQAW";
iommus = <&smmu_700 0x200>;
};
};

25
plat/arm/board/tc/include/platform_def.h
View File

@ -12,7 +12,21 @@
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/board_css_def.h>
#include <plat/arm/board/common/v2m_def.h>
/*
* arm_def.h depends on the platform system counter macros, so must define the
* platform macros before including arm_def.h.
*/
#if TARGET_PLATFORM == 4
#ifdef ARM_SYS_CNTCTL_BASE
#error "error: ARM_SYS_CNTCTL_BASE is defined prior to the PLAT_ARM_SYS_CNTCTL_BASE definition"
#endif
#define PLAT_ARM_SYS_CNTCTL_BASE UL(0x47000000)
#define PLAT_ARM_SYS_CNTREAD_BASE UL(0x47010000)
#endif
#include <plat/arm/common/arm_def.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/arm/css/common/css_def.h>
#include <plat/arm/soc/common/soc_css_def.h>
@ -230,9 +244,9 @@
#if TARGET_PLATFORM <= 2
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
#elif TARGET_PLATFORM == 3
#elif TARGET_PLATFORM >= 3
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#endif /* TARGET_PLATFORM == 3 */
#endif /* TARGET_PLATFORM >= 3 */
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
@ -294,9 +308,9 @@
/* Message Handling Unit (MHU) base addresses */
#if TARGET_PLATFORM <= 2
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#elif TARGET_PLATFORM == 3
#elif TARGET_PLATFORM >= 3
#define PLAT_CSS_MHU_BASE UL(0x46000000)
#endif /* TARGET_PLATFORM == 3 */
#endif /* TARGET_PLATFORM >= 3 */
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* AP<->RSS MHUs */
@ -306,6 +320,9 @@
#elif TARGET_PLATFORM == 3
#define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000)
#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000)
#elif TARGET_PLATFORM == 4
#define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000)
#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49010000)
#endif
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2

4
plat/arm/board/tc/include/tc_helpers.S
View File

@ -81,6 +81,10 @@ func TC_HANDLER(3)
ret
endfunc TC_HANDLER(3)
func TC_HANDLER(4)
ret
endfunc TC_HANDLER(4)
/* -----------------------------------------------------
* void plat_reset_handler(void);
* -----------------------------------------------------

14
plat/arm/board/tc/platform.mk
View File

@ -26,6 +26,9 @@ BRANCH_PROTECTION := 1
ENABLE_FEAT_MPAM := 1 # default is 2, optimise
ENABLE_SVE_FOR_NS := 2 # to show we use it
ENABLE_SVE_FOR_SWD := 1
ENABLE_SME_FOR_NS := 2
ENABLE_SME2_FOR_NS := 2
ENABLE_SME_FOR_SWD := 1
ENABLE_TRBE_FOR_NS := 1
ENABLE_SYS_REG_TRACE_FOR_NS := 1
ENABLE_FEAT_AMU := 1
@ -61,8 +64,8 @@ ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
Some of the features might not work as expected)
endif
ifeq ($(shell expr $(TARGET_PLATFORM) \<= 3), 0)
$(error TARGET_PLATFORM must be less than or equal to 3)
ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0)
$(error TARGET_PLATFORM must be less than or equal to 4)
endif
ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),)
@ -127,6 +130,13 @@ TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_x925.S
endif
# CPU libraries for TARGET_PLATFORM=4
ifeq (${TARGET_PLATFORM}, 4)
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
lib/cpus/aarch64/travis.S
endif
INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c \
plat/arm/common/arm_ni.c

4
plat/arm/board/tc/tc_bl31_setup.c
View File

@ -58,7 +58,7 @@ static scmi_channel_plat_info_t tc_scmi_plat_info = {
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
};
#elif TARGET_PLATFORM == 3
#elif TARGET_PLATFORM >= 3
static scmi_channel_plat_info_t tc_scmi_plat_info = {
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
.db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
@ -66,7 +66,9 @@ static scmi_channel_plat_info_t tc_scmi_plat_info = {
.db_modify_mask = 0x1,
.ring_doorbell = &mhu_ring_doorbell,
};
#endif
#if TARGET_PLATFORM == 3
static void enable_ns_mcn_pmu(void)
{
/*

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