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* changes: feat(tc): bind DPU SMMU on TC4 feat(tc): bind GPU SMMU on TC4 feat(tc): update DT for Drage GPU feat(tc): enable SME and SME2 options for TC4 feat(tc): add new TC4 RoS definitions feat(tc): add system generic timer register definition for TC4 feat(tc): allow TARGET_VERSION=4 feat(tc): add MHUv3 register addresses for TC4 feat(tc): add device tree binding for TC4pull/2005/merge
Manish V Badarkhe
2 months ago
committed by
TrustedFirmware Code Review
TrustedFirmware Code Review
11 changed files with 260 additions and 108 deletions
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/* |
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#define LIT_CAPACITY 239 |
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#define MID_CAPACITY 686 |
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#define BIG_CAPACITY 1024 |
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#define MHU_TX_COMPAT "arm,mhuv3" |
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#define MHU_TX_INT_NAME "" |
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#define MHU_RX_COMPAT "arm,mhuv3" |
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#define MHU_OFFSET 0x10000 |
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#define MHU_MBOX_CELLS 3 |
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#define MHU_RX_INT_NUM 300 |
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#define MHU_RX_INT_NAME "combined-mbx" |
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#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ |
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#define UARTCLK_FREQ 3750000 |
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#if TARGET_FLAVOUR_FVP |
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#define DPU_ADDR 4000000000 |
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#define DPU_IRQ 579 |
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#elif TARGET_FLAVOUR_FPGA |
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#define DPU_ADDR 2cc00000 |
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#define DPU_IRQ 69 |
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#endif |
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#include "tc-base.dtsi" |
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/ { |
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cpus { |
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CPU2:cpu@200 { |
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clocks = <&scmi_dvfs 1>; |
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capacity-dmips-mhz = <MID_CAPACITY>; |
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}; |
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CPU3:cpu@300 { |
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clocks = <&scmi_dvfs 1>; |
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capacity-dmips-mhz = <MID_CAPACITY>; |
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}; |
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CPU6:cpu@600 { |
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clocks = <&scmi_dvfs 2>; |
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capacity-dmips-mhz = <BIG_CAPACITY>; |
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}; |
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CPU7:cpu@700 { |
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clocks = <&scmi_dvfs 2>; |
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capacity-dmips-mhz = <BIG_CAPACITY>; |
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}; |
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}; |
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gic: interrupt-controller@GIC_CTRL_ADDR { |
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ppi-partitions { |
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ppi_partition_little: interrupt-partition-0 { |
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affinity = <&CPU0>, <&CPU1>; |
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}; |
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ppi_partition_mid: interrupt-partition-1 { |
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affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; |
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}; |
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ppi_partition_big: interrupt-partition-2 { |
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affinity = <&CPU6>, <&CPU7>; |
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}; |
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}; |
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}; |
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sram: sram@6000000 { |
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cpu_scp_scmi_p2a: scp-shmem@80 { |
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compatible = "arm,scmi-shmem"; |
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reg = <0x80 0x80>; |
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}; |
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}; |
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firmware { |
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scmi { |
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mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; |
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shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; |
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}; |
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}; |
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}; |
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/* |
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <platform_def.h> |
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#define MHU_TX_ADDR 46240000 /* hex */ |
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#define MHU_RX_ADDR 46250000 /* hex */ |
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#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" |
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#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" |
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#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" |
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#define ETHERNET_ADDR 64000000 |
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#define ETHERNET_INT 799 |
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#define SYS_REGS_ADDR 60080000 |
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#define MMC_ADDR 600b0000 |
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#define MMC_INT_0 778 |
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#define MMC_INT_1 779 |
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#define RTC_ADDR 600a0000 |
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#define RTC_INT 777 |
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#define KMI_0_ADDR 60100000 |
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#define KMI_0_INT 784 |
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#define KMI_1_ADDR 60110000 |
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#define KMI_1_INT 785 |
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#define VIRTIO_BLOCK_ADDR 60020000 |
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#define VIRTIO_BLOCK_INT 769 |
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#include "tc-common.dtsi" |
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#if TARGET_FLAVOUR_FVP |
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#include "tc-fvp.dtsi" |
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#else |
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#include "tc-fpga.dtsi" |
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#endif /* TARGET_FLAVOUR_FVP */ |
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#include "tc3-4-base.dtsi" |
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/ { |
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smmu_700: iommu@3f000000 { |
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status = "okay"; |
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}; |
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smmu_700_dpu: iommu@4002a00000 { |
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status = "okay"; |
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}; |
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dp0: display@DPU_ADDR { |
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iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, |
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<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; |
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}; |
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gpu: gpu@2d000000 { |
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>; |
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interrupt-names = "IRQAW"; |
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iommus = <&smmu_700 0x200>; |
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}; |
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}; |
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