From aaabf9789ae7d73724c43e7225b1313b7e228054 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Thu, 15 Oct 2020 13:40:04 -0500 Subject: [PATCH] Add Makalu CPU lib Add basic support for Makalu CPU. Signed-off-by: John Powell Change-Id: I4e85d425eedea499adf585eb8ab548931185043d --- include/lib/cpus/aarch64/cortex_makalu.h | 23 +++++++ lib/cpus/aarch64/cortex_makalu.S | 77 ++++++++++++++++++++++++ plat/arm/board/arm_fpga/platform.mk | 5 +- plat/arm/board/fvp/platform.mk | 3 +- 4 files changed, 105 insertions(+), 3 deletions(-) create mode 100644 include/lib/cpus/aarch64/cortex_makalu.h create mode 100644 lib/cpus/aarch64/cortex_makalu.S diff --git a/include/lib/cpus/aarch64/cortex_makalu.h b/include/lib/cpus/aarch64/cortex_makalu.h new file mode 100644 index 000000000..4e0dc8625 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_makalu.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_MAKALU_H +#define CORTEX_MAKALU_H + +#define CORTEX_MAKALU_MIDR U(0x410FD4D0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_MAKALU_H */ diff --git a/lib/cpus/aarch64/cortex_makalu.S b/lib/cpus/aarch64/cortex_makalu.S new file mode 100644 index 000000000..98c7d6dfc --- /dev/null +++ b/lib/cpus/aarch64/cortex_makalu.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +func cortex_makalu_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_makalu_reset_func + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_makalu_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_MAKALU_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_MAKALU_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_makalu_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Makalu. Must follow AAPCS. + */ +func cortex_makalu_errata_report + ret +endfunc cortex_makalu_errata_report +#endif + + /* --------------------------------------------- + * This function provides Cortex Makalu-specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_makalu_regs, "aS" +cortex_makalu_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_makalu_cpu_reg_dump + adr x6, cortex_makalu_regs + mrs x8, CORTEX_MAKALU_CPUECTLR_EL1 + ret +endfunc cortex_makalu_cpu_reg_dump + +declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \ + cortex_makalu_reset_func, \ + cortex_makalu_core_pwr_dwn diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index 3ac1c01ab..7bc6a40ba 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2020, Arm Limited. All rights reserved. +# Copyright (c) 2021, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -68,7 +68,8 @@ else lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65ae.S \ lib/cpus/aarch64/cortex_klein.S \ - lib/cpus/aarch64/cortex_matterhorn.S + lib/cpus/aarch64/cortex_matterhorn.S \ + lib/cpus/aarch64/cortex_makalu.S # AArch64/AArch32 cores FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 6c09d7268..3bcfe9168 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -133,6 +133,7 @@ else lib/cpus/aarch64/cortex_a78_ae.S \ lib/cpus/aarch64/cortex_klein.S \ lib/cpus/aarch64/cortex_matterhorn.S \ + lib/cpus/aarch64/cortex_makalu.S \ lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65ae.S endif