diff --git a/Makefile b/Makefile
index f4d623eca..e2922a290 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -153,6 +153,9 @@ ARM_ARCH_MINOR := 5
 ENABLE_FEAT_ECV = 1
 ENABLE_FEAT_FGT = 1
 
+# RME enables CSV2_2 extension by default.
+ENABLE_FEAT_CSV2_2 = 1
+
 endif
 
 # USE_SPINLOCK_CAS requires AArch64 build
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 3bcefdb5d..dab25d681 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -169,7 +169,12 @@ static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_inf
 	state = get_el3state_ctx(ctx);
 	scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
 
-	scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT;
+	scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
+
+#if ENABLE_FEAT_CSV2_2
+	/* Enable access to the SCXTNUM_ELx registers. */
+	scr_el3 |= SCR_EnSCXT_BIT;
+#endif
 
 	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
 }
@@ -222,6 +227,11 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *
 	scr_el3 |= SCR_TERR_BIT;
 #endif
 
+#if ENABLE_FEAT_CSV2_2
+	/* Enable access to the SCXTNUM_ELx registers. */
+	scr_el3 |= SCR_EnSCXT_BIT;
+#endif
+
 #ifdef IMAGE_BL31
 	/*
 	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as