feat(intel): setup SEU ERR read interface for FP8

Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I0618dfcdc86a7c1e0c8047b7214d369866dd2281

plat/intel/soc/common/include/socfpga_mailbox.h

@@ -63,6 +63,9 @@
 #define MBOX_CMD_QSPI_SET_CS				0x34
 #define MBOX_CMD_QSPI_DIRECT				0x3B
 
+/* SEU Commands */
+#define MBOX_CMD_SEU_ERR_READ				0x3C
+
 /* RSU Commands */
 #define MBOX_GET_SUBPARTITION_TABLE			0x5A
 #define MBOX_RSU_STATUS					0x5B
@@ -241,5 +244,6 @@ int mailbox_rsu_update(uint32_t *flash_offset);
 int mailbox_hps_stage_notify(uint32_t execution_stage);
 int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
 int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
+int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
 
 #endif /* SOCFPGA_MBOX_H */

plat/intel/soc/common/include/socfpga_sip_svc.h

@@ -15,6 +15,7 @@
 #define INTEL_SIP_SMC_STATUS_NO_RESPONSE			0x3
 #define INTEL_SIP_SMC_STATUS_ERROR				0x4
 #define INTEL_SIP_SMC_RSU_ERROR					0x7
+#define INTEL_SIP_SMC_SEU_ERR_READ_ERROR		0x8
 
 /* SiP mailbox error code */
 #define GENERIC_RESPONSE_ERROR					0x3FF
@@ -138,6 +139,9 @@
 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT				0xC200008C
 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE				0xC200008E
 
+/* SEU ERR */
+#define INTEL_SIP_SMC_SEU_ERR_STATUS				0xC2000099
+
 #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK				0xF
 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK			0xF
 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET			4U

plat/intel/soc/common/soc/socfpga_mailbox.c

@@ -669,3 +669,10 @@ int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf)
 				CMD_CASUAL, resp_buf,
 				&resp_len);
 }
+
+int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len)
+{
+	return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SEU_ERR_READ, NULL, 0U,
+				CMD_CASUAL, resp_buf,
+				&resp_buf_len);;
+}

plat/intel/soc/common/socfpga_sip_svc.c

@@ -648,6 +648,16 @@ uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
+/* SDM SEU Error services */
+static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz)
+{
+	if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) {
+		return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
+	}
+
+	return INTEL_SIP_SMC_STATUS_OK;
+}
+
 /*
  * This function is responsible for handling all SiP calls from the NS world
  */
@@ -664,7 +674,7 @@ uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
 	uint32_t retval = 0, completed_addr[3];
 	uint32_t retval2 = 0;
 	uint32_t mbox_error = 0;
-	uint64_t retval64, rsu_respbuf[9];
+	uint64_t retval64, rsu_respbuf[9], seu_respbuf[3];
 	int status = INTEL_SIP_SMC_STATUS_OK;
 	int mbox_status;
 	unsigned int len_in_resp;
@@ -1170,6 +1180,15 @@ uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
 					SIP_SVC_VERSION_MAJOR,
 					SIP_SVC_VERSION_MINOR);
 
+	case INTEL_SIP_SMC_SEU_ERR_STATUS:
+		status = intel_sdm_seu_err_read(seu_respbuf,
+					ARRAY_SIZE(seu_respbuf));
+		if (status) {
+			SMC_RET1(handle, status);
+		} else {
+			SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
+		}
+
 	default:
 		return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
 			cookie, handle, flags);