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@ -125,17 +125,13 @@ static void manage_extensions_realm(cpu_context_t *ctx) |
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pmuv3_enable(ctx); |
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/*
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* If SME/SME2 is supported and enabled for NS world, then enables SME |
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* for Realm world. RMM will save/restore required registers that are |
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* shared with SVE/FPU so that Realm can use FPU or SVE. |
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* Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. |
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*/ |
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if (is_feat_sme_supported()) { |
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/* sme_enable() also enables SME2 if supported by hardware */ |
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sme_enable(ctx); |
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} |
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} |
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#if IMAGE_BL31 |
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static void manage_extensions_realm_per_world(void) |
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{ |
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if (is_feat_sve_supported()) { |
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@ -152,8 +148,15 @@ static void manage_extensions_realm_per_world(void) |
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sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); |
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} |
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/*
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* If SME/SME2 is supported and enabled for NS world, then disable trapping |
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* of SME instructions for Realm world. RMM will save/restore required |
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* registers that are shared with SVE/FPU so that Realm can use FPU or SVE. |
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*/ |
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if (is_feat_sme_supported()) { |
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sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); |
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} |
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} |
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#endif /* IMAGE_BL31 */ |
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/*******************************************************************************
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* Jump to the RMM for the first time. |
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