Merge changes from topic "srm/errata" into integration

* changes:
  fix(cpus): workaround for Neoverse V1 errata 2779461
  fix(cpus): workaround for Cortex-A78 erratum 2779479

docs/design/cpu-specific-build-macros.rst

@@ -321,6 +321,10 @@ For Cortex-A78, the following errata build flags are defined :
    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
    it is still open.
 
+-  ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78
+   CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
+   it is still open.
+
 For Cortex-A78 AE, the following errata build flags are defined :
 
 - ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
@@ -468,6 +472,10 @@ For Neoverse V1, the following errata build flags are defined :
    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
    CPU. It is still open.
 
+-  ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1
+   CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
+   CPU. It is still open.
+
 For Cortex-A710, the following errata build flags are defined :
 
 -  ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to

include/lib/cpus/aarch64/cortex_a78.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -40,6 +40,8 @@
 #define CORTEX_A78_ACTLR2_EL1_BIT_2			(ULL(1) << 2)
 #define CORTEX_A78_ACTLR2_EL1_BIT_40			(ULL(1) << 40)
 
+#define CORTEX_A78_ACTLR3_EL1				S3_0_C15_C1_2
+
 /*******************************************************************************
  * CPU Activity Monitor Unit register specific definitions.
  ******************************************************************************/

include/lib/cpus/aarch64/neoverse_v1.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -41,4 +41,6 @@
 #define NEOVERSE_V1_ACTLR2_EL1_BIT_28				(ULL(1) << 28)
 #define NEOVERSE_V1_ACTLR2_EL1_BIT_40				(ULL(1) << 40)
 
+#define NEOVERSE_V1_ACTLR3_EL1					S3_0_C15_C1_2
+
 #endif /* NEOVERSE_V1_H */

lib/cpus/aarch64/cortex_a78.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -351,6 +351,35 @@ func check_errata_2772019
 	b	cpu_rev_var_ls
 endfunc check_errata_2772019
 
+/* ----------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata 2779479.
+ * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
+ * It is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * ----------------------------------------------------
+ */
+func errata_a78_2779479_wa
+	/* Check revision. */
+	mov	x17, x30
+	bl	check_errata_2779479
+	cbz	x0, 1f
+
+	/* Apply the workaround */
+	mrs	x1, CORTEX_A78_ACTLR3_EL1
+	orr	x1, x1, #BIT(47)
+	msr	CORTEX_A78_ACTLR3_EL1, x1
+
+1:
+	ret	x17
+endfunc errata_a78_2779479_wa
+
+func check_errata_2779479
+	/* Applies to r0p0, r1p0, r1p1, r1p2 */
+	mov	x1, #CPU_REV(1, 2)
+	b	cpu_rev_var_ls
+endfunc check_errata_2779479
+
 func check_errata_cve_2022_23960
 #if WORKAROUND_CVE_2022_23960
 	mov	x0, #ERRATA_APPLIES
@@ -414,6 +443,11 @@ func cortex_a78_reset_func
 	bl	errata_a78_2395406_wa
 #endif
 
+#if ERRATA_A78_2779479
+	mov	x0, x18
+	bl	errata_a78_2779479_wa
+#endif
+
 #if ENABLE_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
@@ -493,6 +527,7 @@ func cortex_a78_errata_report
 	report_errata ERRATA_A78_2376745, cortex_a78, 2376745
 	report_errata ERRATA_A78_2395406, cortex_a78, 2395406
 	report_errata ERRATA_A78_2772019, cortex_a78, 2772019
+	report_errata ERRATA_A78_2779479, cortex_a78, 2779479
 	report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
 
 	ldp	x8, x30, [sp], #16

lib/cpus/aarch64/neoverse_v1.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -486,6 +486,35 @@ func check_errata_2743093
 	b	cpu_rev_var_ls
 endfunc check_errata_2743093
 
+	/* ----------------------------------------------------
+ 	 * Errata Workaround for Neoverse V1 Errata #2779461.
+	 * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
+	 * It is still open.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x1, x17
+	 * ----------------------------------------------------
+	 */
+func errata_neoverse_v1_2779461_wa
+	/* Check revision. */
+	mov	x17, x30
+	bl	check_errata_2779461
+	cbz	x0, 1f
+
+	/* Apply the workaround */
+	mrs	x1, NEOVERSE_V1_ACTLR3_EL1
+	orr	x1, x1, #BIT(47)
+	msr	NEOVERSE_V1_ACTLR3_EL1, x1
+
+1:
+	ret	x17
+endfunc errata_neoverse_v1_2779461_wa
+
+func check_errata_2779461
+	/* Applies to r0p0, r1p0, r1p1, r1p2 */
+	mov	x1, #CPU_REV(1, 2)
+	b	cpu_rev_var_ls
+endfunc check_errata_2779461
+
 func check_errata_cve_2022_23960
 #if WORKAROUND_CVE_2022_23960
 	mov	x0, #ERRATA_APPLIES
@@ -544,6 +573,7 @@ func neoverse_v1_errata_report
 	report_errata ERRATA_V1_2294912, neoverse_v1, 2294912
 	report_errata ERRATA_V1_2372203, neoverse_v1, 2372203
 	report_errata ERRATA_V1_2743093, neoverse_v1, 2743093
+	report_errata ERRATA_V1_2779461, neoverse_v1, 2779461
 	report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960
 
 	ldp	x8, x30, [sp], #16
@@ -622,6 +652,11 @@ func neoverse_v1_reset_func
 	bl	errata_neoverse_v1_2372203_wa
 #endif
 
+#if ERRATA_V1_2779461
+	mov	x0, x18
+	bl	errata_neoverse_v1_2779461_wa
+#endif
+
 #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
 	/*
 	 * The Neoverse-V1 generic vectors are overridden to apply errata

lib/cpus/cpu-ops.mk

@@ -362,6 +362,10 @@ ERRATA_A78_2395406	?=0
 # open.
 ERRATA_A78_2772019	?=0
 
+# Flag to apply erratum 2779479 workaround during reset. This erratum applies
+# to revision r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still open.
+ERRATA_A78_2779479	?=0
+
 # Flag to apply erratum 1941500 workaround during reset. This erratum applies
 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
 ERRATA_A78_AE_1941500	?=0
@@ -522,6 +526,11 @@ ERRATA_V1_2372203	?=0
 # still open.
 ERRATA_V1_2743093	?=0
 
+# Flag to apply erratum 2779461 workaround during powerdown. This erratum
+# applies to revisions r0p0, r1p0, r1p1 and r1p2  of the Neoverse V1 cpu and is
+# still open.
+ERRATA_V1_2779461       ?=0
+
 # Flag to apply erratum 1987031 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
 ERRATA_A710_1987031	?=0
@@ -1030,6 +1039,10 @@ $(eval $(call add_define,ERRATA_A78_2395406))
 $(eval $(call assert_boolean,ERRATA_A78_2772019))
 $(eval $(call add_define,ERRATA_A78_2772019))
 
+# Process ERRATA_A78_2779479 flag
+$(eval $(call assert_boolean,ERRATA_A78_2779479))
+$(eval $(call add_define,ERRATA_A78_2779479))
+
 # Process ERRATA_A78_AE_1941500 flag
 $(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
 $(eval $(call add_define,ERRATA_A78_AE_1941500))
@@ -1186,6 +1199,10 @@ $(eval $(call add_define,ERRATA_V1_2372203))
 $(eval $(call assert_boolean,ERRATA_V1_2743093))
 $(eval $(call add_define,ERRATA_V1_2743093))
 
+# Process ERRATA_V1_2779461 flag
+$(eval $(call assert_boolean,ERRATA_V1_2779461))
+$(eval $(call add_define,ERRATA_V1_2779461))
+
 # Process ERRATA_A710_1987031 flag
 $(eval $(call assert_boolean,ERRATA_A710_1987031))
 $(eval $(call add_define,ERRATA_A710_1987031))