From 9d0eed111cb1294605b6d82291fef16a51d35e46 Mon Sep 17 00:00:00 2001 From: Silvano di Ninno Date: Wed, 25 Mar 2020 09:24:51 +0100 Subject: [PATCH] feat(imx8mm): enable optee fdt overlay support Enable optee fdt overlay support. Signed-off-by: Silvano di Ninno Signed-off-by: Jacky Bai Change-Id: I28cb8f744236868727ef4a09d7d2946070404d4d --- plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c | 12 +++++++++--- plat/imx/imx8m/imx8mm/include/platform_def.h | 4 +++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index 628aa2927..debede1fd 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c @@ -152,13 +152,19 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl32_image_ep_info.pc = BL32_BASE; bl32_image_ep_info.spsr = 0; + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; + #ifdef SPD_trusty bl32_image_ep_info.args.arg0 = BL32_SIZE; bl32_image_ep_info.args.arg1 = BL32_BASE; +#else + /* Make sure memory is clean */ + mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); + bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; + bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; #endif - /* Pass TEE base and size to bl33 */ - bl33_image_ep_info.args.arg1 = BL32_BASE; - bl33_image_ep_info.args.arg2 = BL32_SIZE; #endif bl31_tzc380_setup(); diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index 300ef9e62..ed693b9fc 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -59,6 +59,8 @@ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) #define PLAT_NS_IMAGE_SIZE U(0x00200000) +#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) + /* GICv3 base address */ #define PLAT_GICD_BASE U(0x38800000) #define PLAT_GICR_BASE U(0x38880000)