diff --git a/common/feat_detect.c b/common/feat_detect.c index 7f0103741..e6f827c65 100644 --- a/common/feat_detect.c +++ b/common/feat_detect.c @@ -87,7 +87,7 @@ static void read_feat_rme(void) { #if (ENABLE_RME == FEAT_STATE_ALWAYS) feat_detect_panic((get_armv9_2_feat_rme_support() != - ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME"); + RME_NOT_IMPLEMENTED), "RME"); #endif } @@ -129,9 +129,10 @@ void detect_arch_features(void) tainted = false; /* v8.0 features */ - check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1); + check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", + SB_IMPLEMENTED, SB_IMPLEMENTED); check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(), - "CSV2_2", 2, 3); + "CSV2_2", CSV2_2_IMPLEMENTED, CSV2_3_IMPLEMENTED); /* * Even though the PMUv3 is an OPTIONAL feature, it is always * implemented and Arm prescribes so. So assume it will be there and do @@ -142,25 +143,27 @@ void detect_arch_features(void) "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P7); /* v8.1 features */ - check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3); + check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", + PAN_IMPLEMENTED, PAN3_IMPLEMENTED); check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1); /* v8.2 features */ check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(), - "SVE", 1, 1); + "SVE", SVE_IMPLEMENTED, SVE_IMPLEMENTED); check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2); /* v8.3 features */ read_feat_pauth(); /* v8.4 features */ - check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1); + check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", + DIT_IMPLEMENTED, DIT_IMPLEMENTED); check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(), "AMUv1", 1, 2); check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(), "MPAM", 1, 17); check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(), - "NV2", 2, 2); + "NV2", NV2_IMPLEMENTED, NV2_IMPLEMENTED); check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(), "SEL2", 1, 1); check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(), @@ -177,19 +180,22 @@ void detect_arch_features(void) check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(), "AMUv1p1", 2, 2); check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 1); - check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2); + check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", + ECV_IMPLEMENTED, 2); check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(), - "TWED", 1, 1); + "TWED", TWED_IMPLEMENTED, TWED_IMPLEMENTED); /* * even though this is a "DISABLE" it does confusingly perform feature * enablement duties like all other flags here. Check it against the HW * feature when we intend to diverge from the default behaviour */ - check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU", 1, 1); + check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU", + MTPMU_IMPLEMENTED, MTPMU_IMPLEMENTED); /* v8.7 features */ - check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1); + check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", + HCX_IMPLEMENTED, HCX_IMPLEMENTED); /* v8.9 features */ check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(), @@ -207,15 +213,15 @@ void detect_arch_features(void) /* v9.0 features */ check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(), - "BRBE", 1, 2); + "BRBE", BRBE_IMPLEMENTED, 2); check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(), "TRBE", 1, 1); /* v9.2 features */ check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(), - "SME", 1, 2); + "SME", SME_IMPLEMENTED, SME2_IMPLEMENTED); check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(), - "SME2", 2, 2); + "SME2", SME2_IMPLEMENTED, SME2_IMPLEMENTED); /* v9.4 features */ check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1); diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 7e759d819..73b2d7679 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -111,18 +111,18 @@ #define ID_DFR0_PERFMON_PMUV3P5 U(6) #define ID_DFR0_COPTRC_SHIFT U(12) #define ID_DFR0_COPTRC_MASK U(0xf) -#define ID_DFR0_COPTRC_SUPPORTED U(1) +#define COPTRC_IMPLEMENTED U(1) #define ID_DFR0_COPTRC_LENGTH U(4) #define ID_DFR0_TRACEFILT_SHIFT U(28) #define ID_DFR0_TRACEFILT_MASK U(0xf) -#define ID_DFR0_TRACEFILT_SUPPORTED U(1) +#define TRACEFILT_IMPLEMENTED U(1) #define ID_DFR0_TRACEFILT_LENGTH U(4) /* ID_DFR1_EL1 definitions */ #define ID_DFR1_MTPMU_SHIFT U(0) #define ID_DFR1_MTPMU_MASK U(0xf) -#define ID_DFR1_MTPMU_SUPPORTED U(1) -#define ID_DFR1_MTPMU_DISABLED U(15) +#define MTPMU_IMPLEMENTED U(1) +#define MTPMU_NOT_IMPLEMENTED U(15) /* ID_MMFR3 definitions */ #define ID_MMFR3_PAN_SHIFT U(16) @@ -141,14 +141,13 @@ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) #define ID_PFR0_AMU_MASK U(0xf) -#define ID_PFR0_AMU_NOT_SUPPORTED U(0x0) #define ID_PFR0_AMU_V1 U(0x1) #define ID_PFR0_AMU_V1P1 U(0x2) #define ID_PFR0_DIT_SHIFT U(24) #define ID_PFR0_DIT_LENGTH U(4) #define ID_PFR0_DIT_MASK U(0xf) -#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) +#define DIT_IMPLEMENTED (U(1) << ID_PFR0_DIT_SHIFT) /* ID_PFR1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) @@ -166,7 +165,7 @@ /* ID_PFR2 definitions */ #define ID_PFR2_SSBS_SHIFT U(4) #define ID_PFR2_SSBS_MASK U(0xf) -#define SSBS_UNAVAILABLE U(0) +#define SSBS_NOT_IMPLEMENTED U(0) /* SCTLR definitions */ #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h index b52e4d062..c79efc4a6 100644 --- a/include/arch/aarch32/arch_features.h +++ b/include/arch/aarch32/arch_features.h @@ -136,7 +136,7 @@ static inline bool is_feat_pan_present(void) static inline unsigned int is_feat_ssbs_present(void) { return ((read_id_pfr2() >> ID_PFR2_SSBS_SHIFT) & - ID_PFR2_SSBS_MASK) != SSBS_UNAVAILABLE; + ID_PFR2_SSBS_MASK) != SSBS_NOT_IMPLEMENTED; } /* @@ -201,7 +201,7 @@ static inline bool is_feat_mtpmu_supported(void) unsigned int mtpmu = read_feat_mtpmu_id_field(); - return mtpmu != 0U && mtpmu != ID_DFR1_MTPMU_DISABLED; + return ((mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED)); } #endif /* ARCH_FEATURES_H */ diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 697eb82c1..41eeabb5d 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -76,7 +76,7 @@ orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS) ldcopr r1, ID_DFR0 ubfx r1, r1, #ID_DFR0_COPTRC_SHIFT, #ID_DFR0_COPTRC_LENGTH - cmp r1, #ID_DFR0_COPTRC_SUPPORTED + cmp r1, #COPTRC_IMPLEMENTED bne 1f orr r0, r0, #NSTRCDIS_BIT 1: @@ -143,7 +143,7 @@ SDCR_SCCD_BIT) & ~SDCR_TTRF_BIT) ldcopr r1, ID_DFR0 ubfx r1, r1, #ID_DFR0_TRACEFILT_SHIFT, #ID_DFR0_TRACEFILT_LENGTH - cmp r1, #ID_DFR0_TRACEFILT_SUPPORTED + cmp r1, #TRACEFILT_IMPLEMENTED bne 1f orr r0, r0, #SDCR_TTRF_BIT 1: @@ -182,7 +182,7 @@ */ ldcopr r0, ID_PFR0 and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT) - cmp r0, #ID_PFR0_DIT_SUPPORTED + cmp r0, #DIT_IMPLEMENTED bne 1f mrs r0, cpsr orr r0, r0, #CPSR_DIT_BIT diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 5508ebb8f..ea9aa5105 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -179,7 +179,6 @@ #define ID_AA64PFR0_AMU_SHIFT U(44) #define ID_AA64PFR0_AMU_MASK ULL(0xf) -#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) #define ID_AA64PFR0_AMU_V1 ULL(0x1) #define ID_AA64PFR0_AMU_V1P1 U(0x2) @@ -191,8 +190,8 @@ #define ID_AA64PFR0_SVE_SHIFT U(32) #define ID_AA64PFR0_SVE_MASK ULL(0xf) -#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) #define ID_AA64PFR0_SVE_LENGTH U(4) +#define SVE_IMPLEMENTED ULL(0x1) #define ID_AA64PFR0_SEL2_SHIFT U(36) #define ID_AA64PFR0_SEL2_MASK ULL(0xf) @@ -203,23 +202,21 @@ #define ID_AA64PFR0_DIT_SHIFT U(48) #define ID_AA64PFR0_DIT_MASK ULL(0xf) #define ID_AA64PFR0_DIT_LENGTH U(4) -#define ID_AA64PFR0_DIT_SUPPORTED U(1) +#define DIT_IMPLEMENTED ULL(1) #define ID_AA64PFR0_CSV2_SHIFT U(56) #define ID_AA64PFR0_CSV2_MASK ULL(0xf) #define ID_AA64PFR0_CSV2_LENGTH U(4) -#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) -#define ID_AA64PFR0_CSV2_3_SUPPORTED ULL(0x3) +#define CSV2_2_IMPLEMENTED ULL(0x2) +#define CSV2_3_IMPLEMENTED ULL(0x3) #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) -#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) -#define ID_AA64PFR0_FEAT_RME_V1 U(1) +#define RME_NOT_IMPLEMENTED ULL(0) #define ID_AA64PFR0_RAS_SHIFT U(28) #define ID_AA64PFR0_RAS_MASK ULL(0xf) -#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) #define ID_AA64PFR0_RAS_LENGTH U(4) /* Exception level handling */ @@ -230,12 +227,13 @@ /* ID_AA64DFR0_EL1.TraceVer definitions */ #define ID_AA64DFR0_TRACEVER_SHIFT U(4) #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) -#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) #define ID_AA64DFR0_TRACEVER_LENGTH U(4) + #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) -#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) +#define TRACEFILT_IMPLEMENTED ULL(1) + #define ID_AA64DFR0_PMUVER_LENGTH U(4) #define ID_AA64DFR0_PMUVER_SHIFT U(8) #define ID_AA64DFR0_PMUVER_MASK U(0xf) @@ -251,24 +249,24 @@ /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ #define ID_AA64DFR0_PMS_SHIFT U(32) #define ID_AA64DFR0_PMS_MASK ULL(0xf) -#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) -#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) +#define SPE_IMPLEMENTED ULL(0x1) +#define SPE_NOT_IMPLEMENTED ULL(0x0) /* ID_AA64DFR0_EL1.TraceBuffer definitions */ #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) -#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) +#define TRACEBUFFER_IMPLEMENTED ULL(1) /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ #define ID_AA64DFR0_MTPMU_SHIFT U(48) #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) -#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) -#define ID_AA64DFR0_MTPMU_DISABLED ULL(15) +#define MTPMU_IMPLEMENTED ULL(1) +#define MTPMU_NOT_IMPLEMENTED ULL(15) /* ID_AA64DFR0_EL1.BRBE definitions */ #define ID_AA64DFR0_BRBE_SHIFT U(52) #define ID_AA64DFR0_BRBE_MASK ULL(0xf) -#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) +#define BRBE_IMPLEMENTED ULL(1) /* ID_AA64DFR1_EL1 definitions */ #define ID_AA64DFR1_EBEP_SHIFT U(48) @@ -294,8 +292,8 @@ #define ID_AA64ISAR1_SB_SHIFT U(36) #define ID_AA64ISAR1_SB_MASK ULL(0xf) -#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) -#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) +#define SB_IMPLEMENTED ULL(0x1) +#define SB_NOT_IMPLEMENTED ULL(0x0) /* ID_AA64ISAR2_EL1 definitions */ #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 @@ -323,52 +321,41 @@ #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) -#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) -#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) -#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) +#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) +#define ECV_IMPLEMENTED ULL(0x1) #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) -#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) -#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) +#define FGT_IMPLEMENTED ULL(0x1) +#define FGT_NOT_IMPLEMENTED ULL(0x0) #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) -#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) -#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1) -#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) -#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) -#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) -#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) -#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) -#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2) +#define TGRAN16_IMPLEMENTED ULL(0x1) /* ID_AA64MMFR1_EL1 definitions */ #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) -#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) -#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) +#define TWED_IMPLEMENTED ULL(0x1) #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) -#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) -#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) -#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) -#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) +#define PAN_IMPLEMENTED ULL(0x1) +#define PAN2_IMPLEMENTED ULL(0x2) +#define PAN3_IMPLEMENTED ULL(0x3) #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) -#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) -#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) +#define HCX_IMPLEMENTED ULL(0x1) /* ID_AA64MMFR2_EL1 definitions */ #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 @@ -388,9 +375,7 @@ #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) -#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) -#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) -#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) +#define NV2_IMPLEMENTED ULL(0x2) /* ID_AA64MMFR3_EL1 definitions */ #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 @@ -414,11 +399,11 @@ #define ID_AA64PFR1_EL1_BT_SHIFT U(0) #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) -#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ +#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) -#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ +#define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) @@ -434,8 +419,7 @@ #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) #define GCS_IMPLEMENTED ULL(1) -#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) -#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) +#define RNG_TRAP_IMPLEMENTED ULL(0x1) /* ID_AA64PFR2_EL1 definitions */ #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) @@ -468,9 +452,9 @@ #define ID_AA64PFR1_EL1_SME_SHIFT U(24) #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) #define ID_AA64PFR1_EL1_SME_WIDTH U(4) -#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) -#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) -#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) +#define SME_IMPLEMENTED ULL(0x1) +#define SME2_IMPLEMENTED ULL(0x2) +#define SME_NOT_IMPLEMENTED ULL(0x0) /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) @@ -1102,11 +1086,11 @@ /* ID_AA64SMFR0_EL1 definitions */ #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) -#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) +#define SME_FA64_IMPLEMENTED U(0x1) #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) -#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) -#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) +#define SME_INST_IMPLEMENTED ULL(0x0) +#define SME2_INST_IMPLEMENTED ULL(0x1) /* SMCR_ELx definitions */ #define SMCR_ELX_LEN_SHIFT U(0) diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 7582fc65d..7b556cad3 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -113,7 +113,7 @@ static inline unsigned int is_feat_mte2_present(void) static inline bool is_feat_ssbs_present(void) { return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) & - ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_UNAVAILABLE; + ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_NOT_IMPLEMENTED; } static inline bool is_feat_nmi_present(void) @@ -214,7 +214,7 @@ static inline bool is_feat_rng_trap_present(void) { return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) & ID_AA64PFR1_EL1_RNDR_TRAP_MASK) - == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED); + == RNG_TRAP_IMPLEMENTED); } static inline unsigned int get_armv9_2_feat_rme_support(void) @@ -255,9 +255,9 @@ static inline unsigned int read_feat_csv2_id_field(void) } CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field, - ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2) + CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2) CREATE_FEATURE_FUNCS_VER(feat_csv2_3, read_feat_csv2_id_field, - ID_AA64PFR0_CSV2_3_SUPPORTED, ENABLE_FEAT_CSV2_3) + CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3) /* FEAT_SPE: Statistical Profiling Extension */ CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, @@ -285,7 +285,7 @@ CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, /* FEAT_NV2: Enhanced Nested Virtualization */ CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0) CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field, - ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS) + NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS) /* FEAT_BRBE: Branch Record Buffer Extension */ CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, @@ -304,7 +304,7 @@ static inline unsigned int read_feat_sme_fa64_id_field(void) CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, ENABLE_SME_FOR_NS) CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field, - ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS) + SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS) /******************************************************************************* * Function to get hardware granularity support @@ -350,7 +350,7 @@ static inline bool is_feat_mtpmu_supported(void) unsigned int mtpmu = read_feat_mtpmu_id_field(); - return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED); + return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED); } #endif /* ARCH_FEATURES_H */ diff --git a/include/arch/aarch64/el2_common_macros.S b/include/arch/aarch64/el2_common_macros.S index 9609c0d8c..9f82399df 100644 --- a/include/arch/aarch64/el2_common_macros.S +++ b/include/arch/aarch64/el2_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -157,7 +157,7 @@ */ mrs x0, id_aa64pfr0_el1 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH - cmp x0, #ID_AA64PFR0_DIT_SUPPORTED + cmp x0, #DIT_IMPLEMENTED bne 1f mov x0, #DIT_BIT msr DIT, x0 diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 26c757892..1a3e9b672 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -133,7 +133,7 @@ #if ENABLE_FEAT_DIT > 1 cbz x0, 1f #else - cmp x0, #ID_AA64PFR0_DIT_SUPPORTED + cmp x0, #DIT_IMPLEMENTED ASM_ASSERT(eq) #endif diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S index dc704f204..887001900 100644 --- a/lib/cpus/aarch64/cortex_gelas.S +++ b/lib/cpus/aarch64/cortex_gelas.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Arm Limited. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -42,7 +42,7 @@ func cortex_gelas_core_pwr_dwn mrs x0, ID_AA64PFR1_EL1 ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \ #ID_AA64PFR1_EL1_SME_WIDTH - cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED + cmp x0, #SME_NOT_IMPLEMENTED b.eq 1f msr CORTEX_GELAS_SVCRSM, xzr msr CORTEX_GELAS_SVCRZA, xzr diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S index 2abefe944..ba06f557b 100644 --- a/lib/cpus/aarch64/travis.S +++ b/lib/cpus/aarch64/travis.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Arm Limited. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,7 +38,7 @@ func travis_core_pwr_dwn mrs x0, ID_AA64PFR1_EL1 ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \ #ID_AA64PFR1_EL1_SME_WIDTH - cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED + cmp x0, #SME_NOT_IMPLEMENTED b.eq 1f msr TRAVIS_SVCRSM, xzr msr TRAVIS_SVCRZA, xzr diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index bb6a35cf0..60752b5dd 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,7 +30,7 @@ bool xlat_arch_is_granule_size_supported(size_t size) return (tgranx < 8U); } else if (size == PAGE_SIZE_16KB) { tgranx = read_id_aa64mmfr0_el0_tgran16_field(); - return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED); + return (tgranx >= TGRAN16_IMPLEMENTED); } else if (size == PAGE_SIZE_64KB) { tgranx = read_id_aa64mmfr0_el0_tgran64_field(); /* MSB of TGRAN64 field will be '1' for unsupported feature */ diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c index 57d211ed7..545616469 100644 --- a/services/arm_arch_svc/arm_arch_svc_setup.c +++ b/services/arm_arch_svc/arm_arch_svc_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,7 +54,7 @@ static int32_t smccc_arch_features(u_register_t arg1) * If architectural SSBS is available on this PE, no firmware * mitigation via SMCCC_ARCH_WORKAROUND_2 is required. */ - if (ssbs != SSBS_UNAVAILABLE) + if (ssbs != SSBS_NOT_IMPLEMENTED) return 1; /*