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@ -72,10 +72,20 @@ either mandatory or optional. |
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2.1 Common mandatory modifications |
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---------------------------------- |
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A platform port must enable the Memory Management Unit (MMU) with identity |
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mapped page tables, and enable both the instruction and data caches for each BL |
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stage. In ARM standard platforms, each BL stage configures the MMU in |
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the platform-specific architecture setup function, `blX_plat_arch_setup()`. |
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A platform port must enable the Memory Management Unit (MMU) as well as the |
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instruction and data caches for each BL stage. Setting up the translation |
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tables is the responsibility of the platform port because memory maps differ |
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across platforms. A memory translation library (see `lib/aarch64/xlat_helpers.c` |
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and `lib/aarch64/xlat_tables.c`) is provided to help in this setup. Note that |
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although this library supports non-identity mappings, this is intended only for |
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re-mapping peripheral physical addresses and allows platforms with high I/O |
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addresses to reduce their virtual address space. All other addresses |
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corresponding to code and data must currently use an identity mapping. |
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In ARM standard platforms, each BL stage configures the MMU in the |
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platform-specific architecture setup function, `blX_plat_arch_setup()`, and uses |
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an identity mapping for all addresses. |
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If the build option `USE_COHERENT_MEM` is enabled, each platform can allocate a |
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block of identity mapped secure memory with Device-nGnRE attributes aligned to |
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