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@ -619,53 +619,7 @@ int psci_validate_mpidr(u_register_t mpidr) |
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* This function determines the full entrypoint information for the requested |
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* PSCI entrypoint on power on/resume and returns it. |
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******************************************************************************/ |
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#ifdef AARCH32 |
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static int psci_get_ns_ep_info(entry_point_info_t *ep, |
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uintptr_t entrypoint, |
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u_register_t context_id) |
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{ |
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u_register_t ep_attr; |
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unsigned int aif, ee, mode; |
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u_register_t scr = read_scr(); |
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u_register_t ns_sctlr, sctlr; |
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/* Switch to non secure state */ |
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write_scr(scr | SCR_NS_BIT); |
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isb(); |
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ns_sctlr = read_sctlr(); |
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sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; |
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/* Return to original state */ |
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write_scr(scr); |
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isb(); |
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ee = 0; |
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ep_attr = NON_SECURE | EP_ST_DISABLE; |
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if (sctlr & SCTLR_EE_BIT) { |
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ep_attr |= EP_EE_BIG; |
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ee = 1; |
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} |
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SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); |
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ep->pc = entrypoint; |
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zeromem(&ep->args, sizeof(ep->args)); |
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ep->args.arg0 = context_id; |
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mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; |
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/*
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* TODO: Choose async. exception bits if HYP mode is not |
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* implemented according to the values of SCR.{AW, FW} bits |
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*/ |
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aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT; |
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ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif); |
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return PSCI_E_SUCCESS; |
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} |
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#else |
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#ifdef __aarch64__ |
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static int psci_get_ns_ep_info(entry_point_info_t *ep, |
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uintptr_t entrypoint, |
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u_register_t context_id) |
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@ -722,7 +676,53 @@ static int psci_get_ns_ep_info(entry_point_info_t *ep, |
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return PSCI_E_SUCCESS; |
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} |
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#endif |
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#else /* !__aarch64__ */ |
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static int psci_get_ns_ep_info(entry_point_info_t *ep, |
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uintptr_t entrypoint, |
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u_register_t context_id) |
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{ |
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u_register_t ep_attr; |
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unsigned int aif, ee, mode; |
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u_register_t scr = read_scr(); |
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u_register_t ns_sctlr, sctlr; |
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/* Switch to non secure state */ |
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write_scr(scr | SCR_NS_BIT); |
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isb(); |
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ns_sctlr = read_sctlr(); |
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sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; |
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/* Return to original state */ |
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write_scr(scr); |
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isb(); |
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ee = 0; |
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ep_attr = NON_SECURE | EP_ST_DISABLE; |
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if (sctlr & SCTLR_EE_BIT) { |
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ep_attr |= EP_EE_BIG; |
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ee = 1; |
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} |
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SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); |
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ep->pc = entrypoint; |
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zeromem(&ep->args, sizeof(ep->args)); |
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ep->args.arg0 = context_id; |
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mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; |
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/*
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* TODO: Choose async. exception bits if HYP mode is not |
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* implemented according to the values of SCR.{AW, FW} bits |
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*/ |
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aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT; |
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ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif); |
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return PSCI_E_SUCCESS; |
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} |
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#endif /* __aarch64__ */ |
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/*******************************************************************************
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* This function validates the entrypoint with the platform layer if the |
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Alexei Fedorov
5 years ago
TrustedFirmware Code Review