Dimitris Papastamos
7 years ago
committed by
GitHub
GitHub
23 changed files with 1041 additions and 61 deletions
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __EA_HANDLE_H__ |
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#define __EA_HANDLE_H__ |
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/* Constants indicating the reason for an External Abort */ |
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/* External Abort received at SError vector */ |
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#define ERROR_EA_ASYNC 0 |
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/* Synchronous External Abort received at Synchronous exception vector */ |
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#define ERROR_EA_SYNC 1 |
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/* External Abort synchronized by ESB instruction */ |
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#define ERROR_EA_ESB 2 |
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/* RAS event signalled as peripheral interrupt */ |
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#define ERROR_INTERRUPT 3 |
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#endif /* __EA_HANDLE_H__ */ |
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __RAS_COMMON__ |
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#define __RAS_COMMON__ |
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#define ERR_HANDLER_VERSION 1 |
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/* Error record access mechanism */ |
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#define ERR_ACCESS_SYSREG 0 |
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#define ERR_ACCESS_MEMMAP 1 |
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/*
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* Register all error records on the platform. |
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* |
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* This macro must be used in the same file as the array of error record info |
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* are declared. Only then would ARRAY_SIZE() yield a meaningful value. |
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*/ |
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#define REGISTER_ERR_RECORD_INFO(_records) \ |
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const struct err_record_mapping err_record_mapping = { \ |
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.err_records = _records, \ |
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.num_err_records = ARRAY_SIZE(_records), \ |
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} |
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/* Error record info iterator */ |
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#define for_each_err_record_info(_i, _info) \ |
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for (_i = 0, _info = err_record_mapping.err_records; \ |
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_i < err_record_mapping.num_err_records; \ |
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_i++, _info++) |
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#define _ERR_RECORD_COMMON(_probe, _handler, _aux) \ |
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.probe = _probe, \ |
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.handler = _handler, \ |
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.aux_data = _aux, |
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#define ERR_RECORD_SYSREG_V1(_idx_start, _num_idx, _probe, _handler, _aux) \ |
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{ \ |
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.version = 1, \ |
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.sysreg.idx_start = _idx_start, \ |
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.sysreg.num_idx = _num_idx, \ |
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.access = ERR_ACCESS_SYSREG, \ |
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_ERR_RECORD_COMMON(_probe, _handler, _aux) \ |
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} |
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#define ERR_RECORD_MEMMAP_V1(_base_addr, _size_num_k, _probe, _handler, _aux) \ |
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{ \ |
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.version = 1, \ |
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.memmap.base_addr = _base_addr, \ |
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.memmap.size_num_k = _size_num_k, \ |
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.access = ERR_ACCESS_MEMMAP, \ |
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_ERR_RECORD_COMMON(_probe, _handler, _aux) \ |
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} |
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/*
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* Macro to be used to name and declare an array of RAS interrupts along with |
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* their handlers. |
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* |
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* This macro must be used in the same file as the array of interrupts are |
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* declared. Only then would ARRAY_SIZE() yield a meaningful value. Also, the |
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* array is expected to be sorted in the increasing order of interrupt number. |
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*/ |
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#define REGISTER_RAS_INTERRUPTS(_array) \ |
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const struct ras_interrupt_mapping ras_interrupt_mapping = { \ |
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.intrs = _array, \ |
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.num_intrs = ARRAY_SIZE(_array), \ |
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} |
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#ifndef __ASSEMBLY__ |
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#include <assert.h> |
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#include <ras_arch.h> |
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struct err_record_info; |
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struct ras_interrupt { |
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/* Interrupt number, and the associated error record info */ |
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unsigned int intr_number; |
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struct err_record_info *err_record; |
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void *cookie; |
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}; |
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/* Function to probe a error record group for error */ |
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typedef int (*err_record_probe_t)(const struct err_record_info *info, |
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int *probe_data); |
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/* Data passed to error record group handler */ |
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struct err_handler_data { |
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/* Info passed on from top-level exception handler */ |
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uint64_t flags; |
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void *cookie; |
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void *handle; |
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/* Data structure version */ |
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unsigned int version; |
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/* Reason for EA: one the ERROR_* constants */ |
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unsigned int ea_reason; |
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/*
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* For EAs received at vector, the value read from ESR; for an EA |
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* synchronized by ESB, the value of DISR. |
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*/ |
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uint32_t syndrome; |
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/* For errors signalled via. interrupt, the raw interrupt ID; otherwise, 0. */ |
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unsigned int interrupt; |
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}; |
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/* Function to handle error from an error record group */ |
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typedef int (*err_record_handler_t)(const struct err_record_info *info, |
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int probe_data, const struct err_handler_data *const data); |
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/* Error record information */ |
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struct err_record_info { |
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/* Function to probe error record group for errors */ |
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err_record_probe_t probe; |
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/* Function to handle error record group errors */ |
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err_record_handler_t handler; |
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/* Opaque group-specific data */ |
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void *aux_data; |
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/* Additional information for Standard Error Records */ |
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union { |
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struct { |
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/*
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* For a group accessed via. memory-mapped register, |
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* base address of the page hosting error records, and |
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* the size of the record group. |
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*/ |
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uintptr_t base_addr; |
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/* Size of group in number of KBs */ |
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unsigned int size_num_k; |
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} memmap; |
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struct { |
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/*
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* For error records accessed via. system register, index of |
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* the error record. |
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*/ |
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unsigned int idx_start; |
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unsigned int num_idx; |
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} sysreg; |
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}; |
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/* Data structure version */ |
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unsigned int version; |
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/* Error record access mechanism */ |
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unsigned int access:1; |
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}; |
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struct err_record_mapping { |
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struct err_record_info *err_records; |
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size_t num_err_records; |
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}; |
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struct ras_interrupt_mapping { |
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struct ras_interrupt *intrs; |
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size_t num_intrs; |
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}; |
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extern const struct err_record_mapping err_record_mapping; |
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extern const struct ras_interrupt_mapping ras_interrupt_mapping; |
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/*
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* Helper functions to probe memory-mapped and system registers implemented in |
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* Standard Error Record format |
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*/ |
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static inline int ras_err_ser_probe_memmap(const struct err_record_info *info, |
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int *probe_data) |
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{ |
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assert(info->version == ERR_HANDLER_VERSION); |
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return ser_probe_memmap(info->memmap.base_addr, info->memmap.size_num_k, |
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probe_data); |
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} |
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static inline int ras_err_ser_probe_sysreg(const struct err_record_info *info, |
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int *probe_data) |
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{ |
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assert(info->version == ERR_HANDLER_VERSION); |
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return ser_probe_sysreg(info->sysreg.idx_start, info->sysreg.num_idx, |
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probe_data); |
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} |
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int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, |
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void *handle, uint64_t flags); |
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void ras_init(void); |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __RAS_COMMON__ */ |
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@ -0,0 +1,225 @@ |
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __RAS_H__ |
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#define __RAS_H__ |
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#include <arch.h> |
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#include <arch_helpers.h> |
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#include <assert.h> |
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#include <context.h> |
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#include <mmio.h> |
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#include <stdint.h> |
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/*
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* Size of nodes implementing Standard Error Records - currently only 4k is |
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* supported. |
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*/ |
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#define STD_ERR_NODE_SIZE_NUM_K 4 |
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/*
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* Individual register offsets within an error record in Standard Error Record |
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* format when error records are accessed through memory-mapped registers. |
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*/ |
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#define ERR_FR(n) (0x0 + (64 * (n))) |
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#define ERR_CTLR(n) (0x8 + (64 * (n))) |
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#define ERR_STATUS(n) (0x10 + (64 * (n))) |
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#define ERR_ADDR(n) (0x18 + (64 * (n))) |
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#define ERR_MISC0(n) (0x20 + (64 * (n))) |
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#define ERR_MISC1(n) (0x28 + (64 * (n))) |
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/* Group Status Register (ERR_STATUS) offset */ |
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#define ERR_GSR(base, size_num_k, n) \ |
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((base) + (0x380 * (size_num_k)) + (8 * (n))) |
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/* Management register offsets */ |
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#define ERR_DEVID(base, size_num_k) \ |
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((base) + ((0x400 * (size_num_k)) - 0x100) + 0xc8) |
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#define ERR_DEVID_MASK 0xffff |
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/* Standard Error Record status register fields */ |
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#define ERR_STATUS_AV_SHIFT 31 |
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#define ERR_STATUS_AV_MASK U(0x1) |
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#define ERR_STATUS_V_SHIFT 30 |
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#define ERR_STATUS_V_MASK U(0x1) |
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#define ERR_STATUS_UE_SHIFT 29 |
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#define ERR_STATUS_UE_MASK U(0x1) |
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#define ERR_STATUS_ER_SHIFT 28 |
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#define ERR_STATUS_ER_MASK U(0x1) |
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#define ERR_STATUS_OF_SHIFT 27 |
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#define ERR_STATUS_OF_MASK U(0x1) |
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#define ERR_STATUS_MV_SHIFT 26 |
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#define ERR_STATUS_MV_MASK U(0x1) |
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#define ERR_STATUS_CE_SHIFT 24 |
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#define ERR_STATUS_CE_MASK U(0x3) |
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#define ERR_STATUS_DE_SHIFT 23 |
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#define ERR_STATUS_DE_MASK U(0x1) |
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#define ERR_STATUS_PN_SHIFT 22 |
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#define ERR_STATUS_PN_MASK U(0x1) |
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#define ERR_STATUS_UET_SHIFT 20 |
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#define ERR_STATUS_UET_MASK U(0x3) |
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#define ERR_STATUS_IERR_SHIFT 8 |
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#define ERR_STATUS_IERR_MASK U(0xff) |
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#define ERR_STATUS_SERR_SHIFT 0 |
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#define ERR_STATUS_SERR_MASK U(0xff) |
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#define ERR_STATUS_GET_FIELD(_status, _field) \ |
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(((_status) >> ERR_STATUS_ ##_field ##_SHIFT) & ERR_STATUS_ ##_field ##_MASK) |
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#define ERR_STATUS_CLR_FIELD(_status, _field) \ |
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(_status) &= ~(ERR_STATUS_ ##_field ##_MASK << ERR_STATUS_ ##_field ##_SHIFT) |
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#define ERR_STATUS_SET_FIELD(_status, _field, _value) \ |
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(_status) |= (((_value) & ERR_STATUS_ ##_field ##_MASK) << ERR_STATUS_ ##_field ##_SHIFT) |
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#define ERR_STATUS_WRITE_FIELD(_status, _field, _value) do { \ |
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ERR_STATUS_CLR_FIELD(_status, _field, _value); \ |
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ERR_STATUS_SET_FIELD(_status, _field, _value); \ |
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} while (0) |
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/* Standard Error Record control register fields */ |
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#define ERR_CTLR_WDUI_SHIFT 11 |
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#define ERR_CTLR_WDUI_MASK 0x1 |
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#define ERR_CTLR_RDUI_SHIFT 10 |
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#define ERR_CTLR_RDUI_MASK 0x1 |
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#define ERR_CTLR_DUI_SHIFT ERR_CTLR_RDUI_SHIFT |
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#define ERR_CTLR_DUI_MASK ERR_CTLR_RDUI_MASK |
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#define ERR_CTLR_WCFI_SHIFT 9 |
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#define ERR_CTLR_WCFI_MASK 0x1 |
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#define ERR_CTLR_RCFI_SHIFT 8 |
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#define ERR_CTLR_RCFI_MASK 0x1 |
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#define ERR_CTLR_CFI_SHIFT ERR_CTLR_RCFI_SHIFT |
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#define ERR_CTLR_CFI_MASK ERR_CTLR_RCFI_MASK |
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#define ERR_CTLR_WUE_SHIFT 7 |
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#define ERR_CTLR_WUE_MASK 0x1 |
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#define ERR_CTLR_WFI_SHIFT 6 |
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#define ERR_CTLR_WFI_MASK 0x1 |
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#define ERR_CTLR_WUI_SHIFT 5 |
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#define ERR_CTLR_WUI_MASK 0x1 |
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#define ERR_CTLR_RUE_SHIFT 4 |
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#define ERR_CTLR_RUE_MASK 0x1 |
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#define ERR_CTLR_UE_SHIFT ERR_CTLR_RUE_SHIFT |
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#define ERR_CTLR_UE_MASK ERR_CTLR_RUE_MASK |
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#define ERR_CTLR_RFI_SHIFT 3 |
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#define ERR_CTLR_RFI_MASK 0x1 |
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#define ERR_CTLR_FI_SHIFT ERR_CTLR_RFI_SHIFT |
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#define ERR_CTLR_FI_MASK ERR_CTLR_RFI_MASK |
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#define ERR_CTLR_RUI_SHIFT 2 |
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#define ERR_CTLR_RUI_MASK 0x1 |
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#define ERR_CTLR_UI_SHIFT ERR_CTLR_RUI_SHIFT |
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#define ERR_CTLR_UI_MASK ERR_CTLR_RUI_MASK |
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#define ERR_CTLR_ED_SHIFT 0 |
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#define ERR_CTLR_ED_MASK 0x1 |
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#define ERR_CTLR_CLR_FIELD(_ctlr, _field) \ |
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(_ctlr) &= ~(ERR_CTLR_ ##_field _MASK << ERR_CTLR_ ##_field ##_SHIFT) |
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#define ERR_CTLR_SET_FIELD(_ctlr, _field, _value) \ |
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(_ctlr) |= (((_value) & ERR_CTLR_ ##_field ##_MASK) << ERR_CTLR_ ##_field ##_SHIFT) |
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#define ERR_CTLR_ENABLE_FIELD(_ctlr, _field) \ |
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ERR_CTLR_SET_FIELD(_ctlr, _field, ERR_CTLR_ ##_field ##_MASK) |
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/* Uncorrected error types */ |
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#define ERROR_STATUS_UET_UC 0x0 /* Uncontainable */ |
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#define ERROR_STATUS_UET_UEU 0x1 /* Unrecoverable */ |
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#define ERROR_STATUS_UET_UEO 0x2 /* Restable */ |
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#define ERROR_STATUS_UET_UER 0x3 /* Recoverable */ |
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/*
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* Standard Error Record accessors for memory-mapped registers. |
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*/ |
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static inline uint64_t ser_get_feature(uintptr_t base, unsigned int idx) |
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{ |
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return mmio_read_64(base + ERR_FR(idx)); |
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} |
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static inline uint64_t ser_get_control(uintptr_t base, unsigned int idx) |
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{ |
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return mmio_read_64(base + ERR_CTLR(idx)); |
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} |
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static inline uint64_t ser_get_status(uintptr_t base, unsigned int idx) |
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{ |
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return mmio_read_64(base + ERR_STATUS(idx)); |
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} |
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/*
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* Error handling agent would write to the status register to clear an |
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* identified/handled error. Most fields in the status register are |
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* conditional write-one-to-clear. |
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* |
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* Typically, to clear the status, it suffices to write back the same value |
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* previously read. However, if there were new, higher-priority errors recorded |
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* on the node since status was last read, writing read value won't clear the |
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* status. Therefore, an error handling agent must wait on and verify the status |
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* has indeed been cleared. |
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*/ |
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static inline void ser_set_status(uintptr_t base, unsigned int idx, |
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uint64_t status) |
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{ |
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mmio_write_64(base + ERR_STATUS(idx), status); |
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} |
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static inline uint64_t ser_get_addr(uintptr_t base, unsigned int idx) |
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{ |
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return mmio_read_64(base + ERR_ADDR(idx)); |
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} |
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static inline uint64_t ser_get_misc0(uintptr_t base, unsigned int idx) |
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{ |
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return mmio_read_64(base + ERR_MISC0(idx)); |
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} |
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static inline uint64_t ser_get_misc1(uintptr_t base, unsigned int idx) |
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{ |
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return mmio_read_64(base + ERR_MISC1(idx)); |
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} |
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/*
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* Standard Error Record helpers for System registers. |
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*/ |
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static inline void ser_sys_select_record(unsigned int idx) |
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{ |
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unsigned int max_idx __unused = read_erridr_el1() & ERRIDR_MASK; |
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assert(idx < max_idx); |
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write_errselr_el1(idx); |
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isb(); |
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} |
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/* Library functions to probe Standard Error Record */ |
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int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data); |
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int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data); |
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#endif /* __RAS_H__ */ |
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@ -0,0 +1,138 @@ |
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <arch_helpers.h> |
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#include <debug.h> |
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#include <ea_handle.h> |
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#include <ehf.h> |
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#include <platform.h> |
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#include <ras.h> |
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#include <ras_arch.h> |
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#ifndef PLAT_RAS_PRI |
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# error Platform must define RAS priority value |
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#endif |
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/* Handler that receives External Aborts on RAS-capable systems */ |
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int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, |
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void *handle, uint64_t flags) |
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{ |
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unsigned int i, n_handled = 0, ret; |
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int probe_data; |
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struct err_record_info *info; |
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const struct err_handler_data err_data = { |
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.version = ERR_HANDLER_VERSION, |
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.ea_reason = ea_reason, |
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.interrupt = 0, |
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.syndrome = syndrome, |
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.flags = flags, |
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.cookie = cookie, |
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.handle = handle |
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}; |
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for_each_err_record_info(i, info) { |
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assert(info->probe != NULL); |
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assert(info->handler != NULL); |
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/* Continue probing until the record group signals no error */ |
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while (1) { |
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if (info->probe(info, &probe_data) == 0) |
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break; |
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/* Handle error */ |
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ret = info->handler(info, probe_data, &err_data); |
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if (ret != 0) |
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return ret; |
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n_handled++; |
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} |
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} |
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return (n_handled != 0); |
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} |
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#if ENABLE_ASSERTIONS |
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static void assert_interrupts_sorted(void) |
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{ |
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unsigned int i, last; |
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struct ras_interrupt *start = ras_interrupt_mapping.intrs; |
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if (ras_interrupt_mapping.num_intrs == 0) |
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return; |
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last = start[0].intr_number; |
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for (i = 1; i < ras_interrupt_mapping.num_intrs; i++) { |
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assert(start[i].intr_number > last); |
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last = start[i].intr_number; |
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} |
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} |
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#endif |
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/*
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* Given an RAS interrupt number, locate the registered handler and call it. If |
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* no handler was found for the interrupt number, this function panics. |
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*/ |
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static int ras_interrupt_handler(uint32_t intr_raw, uint32_t flags, |
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void *handle, void *cookie) |
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{ |
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struct ras_interrupt *ras_inrs = ras_interrupt_mapping.intrs; |
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struct ras_interrupt *selected = NULL; |
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int start, end, mid, probe_data, ret __unused; |
|||
|
|||
const struct err_handler_data err_data = { |
|||
.version = ERR_HANDLER_VERSION, |
|||
.interrupt = intr_raw, |
|||
.flags = flags, |
|||
.cookie = cookie, |
|||
.handle = handle |
|||
}; |
|||
|
|||
assert(ras_interrupt_mapping.num_intrs > 0); |
|||
|
|||
start = 0; |
|||
end = ras_interrupt_mapping.num_intrs; |
|||
while (start <= end) { |
|||
mid = ((end + start) / 2); |
|||
if (intr_raw == ras_inrs[mid].intr_number) { |
|||
selected = &ras_inrs[mid]; |
|||
break; |
|||
} else if (intr_raw < ras_inrs[mid].intr_number) { |
|||
/* Move left */ |
|||
end = mid - 1; |
|||
} else { |
|||
/* Move right */ |
|||
start = mid + 1; |
|||
} |
|||
} |
|||
|
|||
if (selected == NULL) { |
|||
ERROR("RAS interrupt %u has no handler!\n", intr_raw); |
|||
panic(); |
|||
} |
|||
|
|||
|
|||
ret = selected->err_record->probe(selected->err_record, &probe_data); |
|||
assert(ret != 0); |
|||
|
|||
/* Call error handler for the record group */ |
|||
assert(selected->err_record->handler != NULL); |
|||
selected->err_record->handler(selected->err_record, probe_data, |
|||
&err_data); |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
void ras_init(void) |
|||
{ |
|||
#if ENABLE_ASSERTIONS |
|||
/* Check RAS interrupts are sorted */ |
|||
assert_interrupts_sorted(); |
|||
#endif |
|||
|
|||
/* Register RAS priority handler */ |
|||
ehf_register_priority_handler(PLAT_RAS_PRI, ras_interrupt_handler); |
|||
} |
|||
@ -0,0 +1,76 @@ |
|||
/*
|
|||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
#include <ras_arch.h> |
|||
#include <utils_def.h> |
|||
|
|||
/*
|
|||
* Probe for error in memory-mapped registers containing error records |
|||
* implemented Standard Error Record format. Upon detecting an error, set probe |
|||
* data to the index of the record in error, and return 1; otherwise, return 0. |
|||
*/ |
|||
int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data) |
|||
{ |
|||
int num_records, num_group_regs, i; |
|||
uint64_t gsr; |
|||
|
|||
assert(base != 0); |
|||
|
|||
/* Only 4K supported for now */ |
|||
assert(size_num_k == STD_ERR_NODE_SIZE_NUM_K); |
|||
|
|||
num_records = (mmio_read_32(ERR_DEVID(base, size_num_k)) & ERR_DEVID_MASK); |
|||
|
|||
/* A group register shows error status for 2^6 error records */ |
|||
num_group_regs = (num_records >> 6) + 1; |
|||
|
|||
/* Iterate through group registers to find a record in error */ |
|||
for (i = 0; i < num_group_regs; i++) { |
|||
gsr = mmio_read_64(ERR_GSR(base, size_num_k, i)); |
|||
if (gsr == 0) |
|||
continue; |
|||
|
|||
/* Return the index of the record in error */ |
|||
if (probe_data != NULL) |
|||
*probe_data = ((i << 6) + __builtin_ctz(gsr)); |
|||
|
|||
return 1; |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
/*
|
|||
* Probe for error in System Registers where error records are implemented in |
|||
* Standard Error Record format. Upon detecting an error, set probe data to the |
|||
* index of the record in error, and return 1; otherwise, return 0. |
|||
*/ |
|||
int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data) |
|||
{ |
|||
int i; |
|||
uint64_t status; |
|||
unsigned int max_idx __unused = read_erridr_el1() & ERRIDR_MASK; |
|||
|
|||
assert(idx_start < max_idx); |
|||
assert(check_u32_overflow(idx_start, num_idx) == 0); |
|||
assert((idx_start + num_idx - 1) < max_idx); |
|||
|
|||
for (i = 0; i < num_idx; i++) { |
|||
/* Select the error record */ |
|||
ser_sys_select_record(idx_start + i); |
|||
|
|||
/* Retrieve status register from the error record */ |
|||
status = read_erxstatus_el1(); |
|||
|
|||
/* Check for valid field in status */ |
|||
if (ERR_STATUS_GET_FIELD(status, V)) { |
|||
if (probe_data != NULL) |
|||
*probe_data = i; |
|||
return 1; |
|||
} |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
@ -0,0 +1,16 @@ |
|||
/*
|
|||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#include <ras.h> |
|||
|
|||
struct ras_interrupt arm_ras_interrupts[] = { |
|||
}; |
|||
|
|||
struct err_record_info arm_err_records[] = { |
|||
}; |
|||
|
|||
REGISTER_ERR_RECORD_INFO(arm_err_records); |
|||
REGISTER_RAS_INTERRUPTS(arm_ras_interrupts); |
|||
Loading…
Reference in new issue