From bb273e3be1c4f1cddeac9ceaac95fb56e41e6b98 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 18:58:23 +0900 Subject: [PATCH 01/18] fix(drivers/rcar3): console: fix a return value of console_rcar_init This commit fixes a return value of console_rcar_init because it is expected to return 1 on success but the function always returns 0. Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I97a6800578e3c517c0c1e3c00dc75f0ef75e8778 --- drivers/renesas/common/console/rcar_console.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/renesas/common/console/rcar_console.S b/drivers/renesas/common/console/rcar_console.S index 29baa67a4..b683d7bfb 100644 --- a/drivers/renesas/common/console/rcar_console.S +++ b/drivers/renesas/common/console/rcar_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,7 +63,7 @@ endfunc console_rcar_register * --------------------------------------------- */ func console_rcar_init - mov w0, #0 + mov w0, #1 ret endfunc console_rcar_init From fb3406b6b573cb0b35138ca3c89c5641d3d7b790 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:43:45 +0900 Subject: [PATCH 02/18] fix(plat/rcar3): fix source file to make about GICv2 Changed the plat/renesas/common/common.mk to change the source files about GICv2 by include gicv2.mk, because gic_common.c has deprecated. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: Iaa7eae6b2c1dd79a05339325e6bc422d87bce49e --- plat/renesas/common/common.mk | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk index fafce9834..7f696356c 100644 --- a/plat/renesas/common/common.mk +++ b/plat/renesas/common/common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. +# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -77,9 +77,8 @@ PLAT_INCLUDES := -Iplat/renesas/common/include/registers \ PLAT_BL_COMMON_SOURCES := drivers/renesas/common/iic_dvfs/iic_dvfs.c \ plat/renesas/common/rcar_common.c -RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ +include drivers/arm/gic/v2/gicv2.mk +RCAR_GIC_SOURCES := ${GICV2_SOURCES} \ plat/common/plat_gicv2.c BL2_SOURCES += ${RCAR_GIC_SOURCES} \ From c3d192b8e52823dcbc32e21e47c30693d38bb49f Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:18:57 +0900 Subject: [PATCH 03/18] fix(plat/rcar3): fix version judgment for R-Car D3 Added the process of judgment and logging for R-Car D3 Ver.1.1 and Ver.1.0. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I326aa42374b70b6a4a71893561a7eaa0b6eddef0 --- plat/renesas/common/include/rcar_def.h | 2 ++ plat/renesas/rcar/bl2_plat_setup.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h index 93a65f1a4..9201b6e21 100644 --- a/plat/renesas/common/include/rcar_def.h +++ b/plat/renesas/common/include/rcar_def.h @@ -151,6 +151,8 @@ /* Product register */ #define RCAR_PRR U(0xFFF00044) #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ +#define RCAR_D3_CUT_VER10 U(0x00000000) /* D3 Ver.1.0 */ +#define RCAR_D3_CUT_VER11 U(0x00000010) /* D3 Ver.1.1 */ #define RCAR_MAJOR_MASK U(0x000000F0) #define RCAR_MINOR_MASK U(0x0000000F) #define PRR_PRODUCT_SHIFT U(8) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 41b2d11e7..4c5dcd082 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -897,6 +897,14 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, str, (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); } + } else if (product == PRR_PRODUCT_D3) { + if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) { + NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str); + } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) { + NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str); + } else { + NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str); + } } else { major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; major = major + RCAR_MAJOR_OFFSET; From 77ab3661e55c39694c7ee81de2d1615775711b64 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:25:09 +0900 Subject: [PATCH 04/18] fix(plat/rcar3): fix eMMC boot support for R-Car D3 Fix to support of booting from eMMC (50MHz x 8) on Draak board for R-Car D3. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I0ab2b5c7f8075acbf5f4a69694fb535dddc1a4c8 --- plat/renesas/rcar/bl2_plat_setup.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 4c5dcd082..001347ff9 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -976,10 +976,6 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, str = boot_emmc25x1; break; case MODEMR_BOOT_DEV_EMMC_50X8: -#if RCAR_LSI == RCAR_D3 - ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); - panic(); -#endif str = boot_emmc50x8; break; default: From a8c0c3e9d0df2215ed3b9ef66f4596787d957566 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:39:19 +0900 Subject: [PATCH 05/18] fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3 Fix disabling MFIS write protection for R-Car D3. Signed-off-by: Koichi Yamaguchi Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I8bb5787c09c53dff55d6de89adfcb71157533976 --- plat/renesas/rcar/bl2_plat_setup.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 001347ff9..eebd5af87 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -263,9 +263,6 @@ void bl2_plat_flush_bl31_params(void) if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) goto tlb; - if (product == PRR_PRODUCT_D3) - goto tlb; - /* Disable MFIS write protection */ mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); From 2892fedaf27d8bbc68780a4a2c506c768e81b9f1 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:28:58 +0900 Subject: [PATCH 06/18] feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537 Apply ERRATA_A53_1530924 and ERRATA_A57_1319537. Signed-off-by: Koichi Yamaguchi Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Signed-off-by: Marek Vasut # Drop Makefile header change, reword commit message Change-Id: I7d6e7e40bad6545a1d96470ce1a6e2d04e042670 --- plat/renesas/common/common.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk index 7f696356c..0d88d658e 100644 --- a/plat/renesas/common/common.mk +++ b/plat/renesas/common/common.mk @@ -65,10 +65,12 @@ $(eval $(call add_define,RCAR_CUT_30)) ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 +ERRATA_A53_1530924 := 1 # Enable workarounds for selected Cortex-A57 erratas. ERRATA_A57_859972 := 1 ERRATA_A57_813419 := 1 +ERRATA_A57_1319537 := 1 PLAT_INCLUDES := -Iplat/renesas/common/include/registers \ -Iplat/renesas/common/include \ From 42ffd279dd1a686b19e2f1b69d2e35413d5efeba Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:05:06 +0900 Subject: [PATCH 07/18] feat(plat/rcar3): use PRR cut to determine DRAM size on M3 The new M3 DRAM size can be determined by the PRR cut version. Read the PRR cut version, and if it is older than cut 30, use legacy DRAM size scheme, else report 8GB in 2GBx4 2ch split. Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Signed-off-by: Marek Vasut # Fix DRAM size judgment by PRR register, reword commit message Change-Id: Ib83176d0d09cab5cae0119ba462e42c66c642798 --- plat/renesas/rcar/bl2_plat_setup.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index eebd5af87..3bd20e230 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -705,6 +705,7 @@ static void bl2_advertise_dram_size(uint32_t product) [4] = 0x600000000ULL, [6] = 0x700000000ULL, }; + uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; switch (product) { case PRR_PRODUCT_H3: @@ -730,15 +731,21 @@ static void bl2_advertise_dram_size(uint32_t product) break; case PRR_PRODUCT_M3: + if (cut < PRR_PRODUCT_30) { #if (RCAR_GEN3_ULCB == 1) - /* 2GB(1GBx2 2ch split) */ - dram_config[1] = 0x40000000ULL; - dram_config[5] = 0x40000000ULL; + /* 2GB(1GBx2 2ch split) */ + dram_config[1] = 0x40000000ULL; + dram_config[5] = 0x40000000ULL; #else - /* 4GB(2GBx2 2ch split) */ - dram_config[1] = 0x80000000ULL; - dram_config[5] = 0x80000000ULL; + /* 4GB(2GBx2 2ch split) */ + dram_config[1] = 0x80000000ULL; + dram_config[5] = 0x80000000ULL; #endif + } else { + /* 8GB(2GBx4 2ch split) */ + dram_config[1] = 0x100000000ULL; + dram_config[5] = 0x100000000ULL; + } break; case PRR_PRODUCT_M3N: From a4d821a5a625d941f95ec39fb51ac4fc07c46c5c Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 18:43:26 +0900 Subject: [PATCH 08/18] feat(plat/rcar3): change the memory map for OP-TEE The memory area size of OP-TEE was changed from 1MB to 2MB because the size of OP-TEE has increased. Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: Ic8a165c83a3a9ef2829f68d5fabeed9ccb6da95e --- plat/renesas/common/include/platform_def.h | 4 ++-- tools/renesas/rcar_layout_create/sa6.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/plat/renesas/common/include/platform_def.h b/plat/renesas/common/include/platform_def.h index 72c768891..1213a3c96 100644 --- a/plat/renesas/common/include/platform_def.h +++ b/plat/renesas/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -144,7 +144,7 @@ ******************************************************************************/ #ifndef SPD_NONE #define BL32_BASE U(0x44100000) -#define BL32_LIMIT (BL32_BASE + U(0x100000)) +#define BL32_LIMIT (BL32_BASE + U(0x200000)) #endif /******************************************************************************* diff --git a/tools/renesas/rcar_layout_create/sa6.c b/tools/renesas/rcar_layout_create/sa6.c index fa828b9ac..8fafdaded 100644 --- a/tools/renesas/rcar_layout_create/sa6.c +++ b/tools/renesas/rcar_layout_create/sa6.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -96,7 +96,7 @@ #define RCAR_BL32DST_ADDRESS (0x44100000U) #define RCAR_BL32DST_ADDRESSH (0x00000000U) /* Destination size for BL32 */ -#define RCAR_BL32DST_SIZE (0x00040000U) +#define RCAR_BL32DST_SIZE (0x00080000U) /* Destination address for BL33 */ #define RCAR_BL33DST_ADDRESS (0x50000000U) #define RCAR_BL33DST_ADDRESSH (0x00000000U) From 63a7a34706eedba4d13ce6fc661a634801cf8909 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:13:17 +0900 Subject: [PATCH 09/18] feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up Added the process of SYSECEXTMASK bit set/clear for following power Resume/Shutoff flow. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b --- drivers/renesas/common/pwrc/pwrc.c | 22 ++++++++++++++++++++++ plat/renesas/common/include/rcar_def.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/drivers/renesas/common/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c index 3f60fe633..d29a0267c 100644 --- a/drivers/renesas/common/pwrc/pwrc.c +++ b/drivers/renesas/common/pwrc/pwrc.c @@ -44,6 +44,7 @@ RCAR_INSTANTIATE_LOCK #define CPU_PWR_OFF (0x00000003U) #define RCAR_PSTR_MASK (0x00000003U) #define ST_ALL_STANDBY (0x00003333U) +#define SYSCEXTMASK_EXTMSK0 (0x00000001U) /* Suspend to ram */ #define DBSC4_REG_BASE (0xE6790000U) #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U) @@ -191,6 +192,8 @@ static void scu_power_up(uint64_t mpidr) { uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer; uint32_t c, sysc_reg_bit; + uint32_t lsi_product; + uint32_t lsi_cut; c = rcar_pwrc_get_mpidr_cluster(mpidr); reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR; @@ -205,6 +208,17 @@ static void scu_power_up(uint64_t mpidr) if (mmio_read_32(reg_cpumcr) != 0) mmio_write_32(reg_cpumcr, 0); + lsi_product = mmio_read_32((uintptr_t)RCAR_PRR); + lsi_cut = lsi_product & PRR_CUT_MASK; + lsi_product &= PRR_PRODUCT_MASK; + + if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) || + lsi_product == PRR_PRODUCT_H3 || + lsi_product == PRR_PRODUCT_M3N || + lsi_product == PRR_PRODUCT_E3) { + mmio_setbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0); + } + mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit); mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit); @@ -217,6 +231,14 @@ static void scu_power_up(uint64_t mpidr) while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0) ; mmio_write_32(RCAR_SYSCISR, sysc_reg_bit); + + if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) || + lsi_product == PRR_PRODUCT_H3 || + lsi_product == PRR_PRODUCT_M3N || + lsi_product == PRR_PRODUCT_E3) { + mmio_clrbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0); + } + while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0) ; } diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h index 9201b6e21..2cd26edbf 100644 --- a/plat/renesas/common/include/rcar_def.h +++ b/plat/renesas/common/include/rcar_def.h @@ -148,6 +148,8 @@ #define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */ #define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */ #define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */ +#define RCAR_SYSCEXTMASK U(0xE61802F8) /* External Request Mask */ + /* H3/H3-N, M3 v3.0, M3-N, E3 */ /* Product register */ #define RCAR_PRR U(0xFFF00044) #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ From d10f87674ecee54cffe1ab554cc05733fd16c7f0 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:14:11 +0900 Subject: [PATCH 10/18] feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR Modified the operation register to clearing the state bit of the SYSCISR register from SYSCISR to SYSCISCR. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I9a0820b6414425fa2f4197f60852137827414a4d --- drivers/renesas/common/pwrc/pwrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/renesas/common/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c index d29a0267c..4ebf04906 100644 --- a/drivers/renesas/common/pwrc/pwrc.c +++ b/drivers/renesas/common/pwrc/pwrc.c @@ -230,7 +230,7 @@ static void scu_power_up(uint64_t mpidr) while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0) ; - mmio_write_32(RCAR_SYSCISR, sysc_reg_bit); + mmio_write_32(RCAR_SYSCISCR, sysc_reg_bit); if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) || lsi_product == PRR_PRODUCT_H3 || From 7d58aed3b05fa8c677a7c823c1ca5017a462a3d3 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:17:12 +0900 Subject: [PATCH 11/18] feat(plat/rcar3): add process to back up X6 and X7 register's value Because the x6 and x7 registers will be overwritten by the callee function, added the processing the register's value push to/pop from stack memory. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I5351a008d3b208a30a8bc8651b8d9b4d1a02a8e8 --- plat/renesas/common/aarch64/plat_helpers.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/plat/renesas/common/aarch64/plat_helpers.S b/plat/renesas/common/aarch64/plat_helpers.S index ec21f2510..21c3bedaf 100644 --- a/plat/renesas/common/aarch64/plat_helpers.S +++ b/plat/renesas/common/aarch64/plat_helpers.S @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -284,7 +284,11 @@ func plat_crash_console_putc str x3, [sp, #-16]! str x4, [sp, #-16]! str x5, [sp, #-16]! + str x6, [sp, #-16]! + str x7, [sp, #-16]! bl console_rcar_putc + ldr x7, [sp], #16 + ldr x6, [sp], #16 ldr x5, [sp], #16 ldr x4, [sp], #16 ldr x3, [sp], #16 From 14f0a0817297905c03ddf2c4c6040482ef71d744 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:19:39 +0900 Subject: [PATCH 12/18] feat(plat/rcar3): add process of SSCG setting for R-Car D3 - Added the condition where output the SSCG (MD12) setting to log for R-Car D3. - Added the process to switching the bit rate of SCIF by the SSCG (MD12) setting value for R-Car D3. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9 --- drivers/renesas/common/scif/scif.S | 26 +++++++++++++++++++------- plat/renesas/rcar/bl2_plat_setup.c | 2 +- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/renesas/common/scif/scif.S b/drivers/renesas/common/scif/scif.S index beb8dd838..72b5b4bea 100644 --- a/drivers/renesas/common/scif/scif.S +++ b/drivers/renesas/common/scif/scif.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,7 +79,7 @@ SCSMR_STOP_1 + \ SCSMR_CKS_DIV1) #define SCBRR_115200BPS (17) -#define SCBRR_115200BPSON (16) +#define SCBRR_115200BPS_D3_SSCG (16) #define SCBRR_115200BPS_E3_SSCG (15) #define SCBRR_230400BPS (8) @@ -216,26 +216,38 @@ func console_rcar_init and w1, w1, #PRR_PRODUCT_MASK mov w2, #PRR_PRODUCT_D3 cmp w1, w2 - beq 4f + beq 5f and w1, w1, #PRR_PRODUCT_MASK mov w2, #PRR_PRODUCT_E3 cmp w1, w2 - bne 5f + bne 4f + /* When SSCG(MD12) on (E3) */ ldr x1, =RST_MODEMR ldr w1, [x1] and w1, w1, #MODEMR_MD12 mov w2, #MODEMR_MD12 cmp w1, w2 - bne 5f + bne 4f + /* When SSCG(MD12) on (E3) */ mov w1, #SCBRR_115200BPS_E3_SSCG b 2f 5: - mov w1, #SCBRR_115200BPS + /* In case of D3 */ + ldr x1, =RST_MODEMR + ldr w1, [x1] + and w1, w1, #MODEMR_MD12 + mov w2, #MODEMR_MD12 + cmp w1, w2 + bne 4f + + /* When SSCG(MD12) on (D3) */ + mov w1, #SCBRR_115200BPS_D3_SSCG b 2f 4: - mov w1, #SCBRR_115200BPSON + /* In case of H3/M3/M3N or when SSCG(MD12) is off in E3/D3 */ + mov w1, #SCBRR_115200BPS b 2f 3: mov w1, #SCBRR_230400BPS diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 3bd20e230..e07b96f56 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -916,7 +916,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); } - if (product == PRR_PRODUCT_E3) { + if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) { reg = mmio_read_32(RCAR_MODEMR); sscg = reg & RCAR_SSCG_MASK; str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; From 71f2239f53cd3137ad6abdaf0334dc53f2f21cb1 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:20:24 +0900 Subject: [PATCH 13/18] feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3 Because the Realtime module stop control register n (RMSTPCRn) are not supported in R-Car D3. Therefore, remove access to these registers in R-Car D3. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I4647e28d0e176ff97151e9842019ba12cefe5c03 --- plat/renesas/common/bl2_cpg_init.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/plat/renesas/common/bl2_cpg_init.c b/plat/renesas/common/bl2_cpg_init.c index ba8e53b58..a6579ebcd 100644 --- a/plat/renesas/common/bl2_cpg_init.c +++ b/plat/renesas/common/bl2_cpg_init.c @@ -40,7 +40,6 @@ static void bl2_system_cpg_init_e3(void); #endif #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3) -static void bl2_realtime_cpg_init_d3(void); static void bl2_system_cpg_init_d3(void); #endif @@ -292,23 +291,6 @@ static void bl2_system_cpg_init_e3(void) #endif #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3) -static void bl2_realtime_cpg_init_d3(void) -{ - /* Realtime Module Stop Control Registers */ - cpg_write(RMSTPCR0, 0x00010000U); - cpg_write(RMSTPCR1, 0xFFFFFFFFU); - cpg_write(RMSTPCR2, 0x00060FDCU); - cpg_write(RMSTPCR3, 0xFFFFFFDFU); - cpg_write(RMSTPCR4, 0x80000184U); - cpg_write(RMSTPCR5, 0x83FFFFFFU); - cpg_write(RMSTPCR6, 0xFFFFFFFFU); - cpg_write(RMSTPCR7, 0xFFFFFFFFU); - cpg_write(RMSTPCR8, 0x00F1FFF7U); - cpg_write(RMSTPCR9, 0xF3F5E016U); - cpg_write(RMSTPCR10, 0xFFFEFFE0U); - cpg_write(RMSTPCR11, 0x000000B7U); -} - static void bl2_system_cpg_init_d3(void) { /* System Module Stop Control Registers */ @@ -356,7 +338,7 @@ void bl2_cpg_init(void) bl2_realtime_cpg_init_e3(); break; case PRR_PRODUCT_D3: - bl2_realtime_cpg_init_d3(); + /* no need */ break; default: panic(); @@ -373,7 +355,7 @@ void bl2_cpg_init(void) #elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E bl2_realtime_cpg_init_e3(); #elif RCAR_LSI == RCAR_D3 - bl2_realtime_cpg_init_d3(); + /* no need */ #else #error "Don't have CPG initialize routine(unknown)." #endif From 042d710d1d917357c5142b340c79978264d3afb1 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:21:38 +0900 Subject: [PATCH 14/18] feat(plat/rcar3): update DDR setting for R-Car D3 Update R-Car D3 DDR setting rev.0.02. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I3e3a202fbb0ff1f0f38a968ab5f8633604a46432 --- .../renesas/common/ddr/ddr_a/ddr_init_d3.c | 74 ++++++++++++++----- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c index a49510ed5..f0113f111 100644 --- a/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c +++ b/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -11,7 +11,11 @@ #include "rcar_def.h" #include "../ddr_regs.h" -#define RCAR_DDR_VERSION "rev.0.01" +#define RCAR_DDR_VERSION "rev.0.02" + +/* Average periodic refresh interval[ns]. Support 3900,7800 */ +#define REFRESH_RATE 3900 + #if RCAR_LSI != RCAR_D3 #error "Don't have DDR initialize routine." @@ -44,7 +48,7 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBTR16, 0x09210507); mmio_write_32(DBSC_DBTR17, 0x040E0000); mmio_write_32(DBSC_DBTR18, 0x00000200); - mmio_write_32(DBSC_DBTR19, 0x012B004B); + mmio_write_32(DBSC_DBTR19, 0x0129004B); mmio_write_32(DBSC_DBTR20, 0x020000FB); mmio_write_32(DBSC_DBTR21, 0x00040004); mmio_write_32(DBSC_DBBL, 0x00000000); @@ -54,8 +58,8 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); - mmio_write_32(DBSC_SCFCTST0, 0x0D020D04); - mmio_write_32(DBSC_SCFCTST1, 0x0306040C); + mmio_write_32(DBSC_SCFCTST0, 0x0C050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0305030C); mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); @@ -101,7 +105,9 @@ static void init_ddr_d3_1866(void) ; mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89); + mmio_write_32(DBSC_DBPDRGD_0, + (uint32_t) (REFRESH_RATE * 928 / 125) - 400 + + 0x0A300000); mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); @@ -117,7 +123,11 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0); + if (REFRESH_RATE > 3900) { + mmio_write_32(DBSC_DBPDRGD_0, 0x00000020); + } else { + mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0); + } mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); @@ -225,8 +235,10 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); r2 = mmio_read_32(DBSC_DBPDRGD_0); mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); @@ -296,8 +308,10 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - mmio_write_32(DBSC_DBCALCNF, 0x0100401B); - mmio_write_32(DBSC_DBRFCNF1, 0x00080E23); + mmio_write_32(DBSC_DBCALCNF, + (uint32_t) (64000000 / REFRESH_RATE) + 0x01000000); + mmio_write_32(DBSC_DBRFCNF1, + (uint32_t) (REFRESH_RATE * 116 / 125) + 0x00080000); mmio_write_32(DBSC_DBRFCNF2, 0x00010000); mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); @@ -346,6 +360,19 @@ static void init_ddr_d3_1600(void) { uint32_t i, r2, r3, r5, r6, r7, r12; + mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); + mmio_write_32(CPG_CPGWPCR, 0xA5A50000); + + mmio_write_32(CPG_SRCR4, 0x20000000); + + mmio_write_32(0xE61500DC, 0xe2200000); + while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) + ; + + mmio_write_32(CPG_SRSTCLR4, 0x20000000); + + mmio_write_32(CPG_CPGWPCR, 0xA5A50001); + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); mmio_write_32(DBSC_DBKIND, 0x00000007); mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); @@ -363,14 +390,14 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBTR10, 0x0000000C); mmio_write_32(DBSC_DBTR11, 0x0000000A); mmio_write_32(DBSC_DBTR12, 0x00120012); - mmio_write_32(DBSC_DBTR13, 0x000000D0); + mmio_write_32(DBSC_DBTR13, 0x000000CE); mmio_write_32(DBSC_DBTR14, 0x00140005); mmio_write_32(DBSC_DBTR15, 0x00050004); mmio_write_32(DBSC_DBTR16, 0x071F0305); mmio_write_32(DBSC_DBTR17, 0x040C0000); mmio_write_32(DBSC_DBTR18, 0x00000200); mmio_write_32(DBSC_DBTR19, 0x01000040); - mmio_write_32(DBSC_DBTR20, 0x020000D8); + mmio_write_32(DBSC_DBTR20, 0x020000D6); mmio_write_32(DBSC_DBTR21, 0x00040004); mmio_write_32(DBSC_DBBL, 0x00000000); mmio_write_32(DBSC_DBODT0, 0x00000001); @@ -379,8 +406,8 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); - mmio_write_32(DBSC_SCFCTST0, 0x0D020C04); - mmio_write_32(DBSC_SCFCTST1, 0x0305040C); + mmio_write_32(DBSC_SCFCTST0, 0x0D050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0306030C); mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); @@ -426,13 +453,14 @@ static void init_ddr_d3_1600(void) ; mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0); + mmio_write_32(DBSC_DBPDRGD_0, + (uint32_t) (REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); @@ -442,7 +470,11 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000098); + if (REFRESH_RATE > 3900) { + mmio_write_32(DBSC_DBPDRGD_0, 0x00000018); + } else { + mmio_write_32(DBSC_DBPDRGD_0, 0x00000098); + } mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); @@ -549,9 +581,11 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); @@ -620,8 +654,10 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - mmio_write_32(DBSC_DBCALCNF, 0x0100401B); - mmio_write_32(DBSC_DBRFCNF1, 0x00080C30); + mmio_write_32(DBSC_DBCALCNF, + (uint32_t) (64000000 / REFRESH_RATE) + 0x01000000); + mmio_write_32(DBSC_DBRFCNF1, + (uint32_t) (REFRESH_RATE * 99 / 125) + 0x00080000); mmio_write_32(DBSC_DBRFCNF2, 0x00010000); mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); @@ -693,7 +729,7 @@ int32_t rcar_dram_init(void) ddr_mbps = 1600; } - NOTICE("BL2: DDR%d\n", ddr_mbps); + NOTICE("BL2: DDR%d(%s)\n", ddr_mbps, RCAR_DDR_VERSION); return 0; } From 053c134683cf74fbf4efad311815b806821f1436 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:22:29 +0900 Subject: [PATCH 15/18] feat(plat/rcar3): modify SWDT counter setting for R-Car D3 Modified the SWDT counter setting for R-Car D3. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: If1fa12bf644486f3fad3c6b54cda6c4cbb604103 --- drivers/renesas/common/watchdog/swdt.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/renesas/common/watchdog/swdt.c b/drivers/renesas/common/watchdog/swdt.c index 1a351ca17..29ef6f430 100644 --- a/drivers/renesas/common/watchdog/swdt.c +++ b/drivers/renesas/common/watchdog/swdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -78,7 +78,7 @@ static void swdt_disable(void) void rcar_swdt_init(void) { uint32_t rmsk, sr; -#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RZ_G2E) +#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RZ_G2E) uint32_t reg, val, product_cut, chk_data; reg = mmio_read_32(RCAR_PRR); @@ -96,6 +96,8 @@ void rcar_swdt_init(void) #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E) mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k); +#elif (RCAR_LSI == RCAR_D3) + mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_8p13k); #else val = WTCNT_UPPER_BYTE; From 5460f82806752e419fdd6862e8ca9c5fefbee3f2 Mon Sep 17 00:00:00 2001 From: Toshiyuki Ogasahara Date: Mon, 12 Jul 2021 19:24:29 +0900 Subject: [PATCH 16/18] feat(plat/rcar3): modify LifeC register setting for R-Car D3 Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3. Signed-off-by: Hideyuki Nitta Signed-off-by: Toshiyuki Ogasahara Signed-off-by: Yoshifumi Hosoya Change-Id: I3f173ac44c11743965c013ef238748b0dc8cabab --- plat/renesas/common/bl2_secure_setting.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/renesas/common/bl2_secure_setting.c b/plat/renesas/common/bl2_secure_setting.c index 095d1f62a..2f8b0011d 100644 --- a/plat/renesas/common/bl2_secure_setting.c +++ b/plat/renesas/common/bl2_secure_setting.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -49,10 +49,10 @@ static const struct { /* * Bit13: SCEG PKA (secure APB) slave ports * 0: registers accessed from secure resource only - * 1: Reserved[R-Car E3] + * 1: Reserved[R-Car E3/D3] * Bit12: SCEG PKA (public APB) slave ports * 0: registers accessed from secure resource only - * 1: Reserved[R-Car E3] + * 1: Reserved[R-Car E3/D3] * Bit10: SCEG Secure Core slave ports * 0: registers accessed from secure resource only */ @@ -152,14 +152,14 @@ static const struct { * Security group 1 attribute setting for slave ports 6 * Bit13: SCEG PKA (secure APB) slave ports * SecurityGroup3 - * Reserved[R-Car E3] + * Reserved[R-Car E3/D3] * Bit12: SCEG PKA (public APB) slave ports * SecurityGroup3 - * Reserved[R-Car E3] + * Reserved[R-Car E3/D3] * Bit10: SCEG Secure Core slave ports * SecurityGroup3 */ -#if RCAR_LSI == RCAR_E3 +#if RCAR_LSI == RCAR_E3 || RCAR_LSI == RCAR_D3 { SEC_GRP0COND6, 0x00000400U }, { SEC_GRP1COND6, 0x00000400U }, #else /* RCAR_LSI == RCAR_E3 */ From 993d809cc115ce23dd2df1df19dc8bb548cc19cd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Mar 2021 00:55:48 +0100 Subject: [PATCH 17/18] feat(drivers/rcar3): add extra offset if booting B-side In case MFISBTSTSR bit 4 is 1, that means the loader was started as B-side. Load the remaining boot components from 8 MiB offset. Signed-off-by: Marek Vasut Change-Id: I11d882f30ca4f0cf55fd28d3470ff1063d350d10 --- drivers/renesas/common/io/io_rcar.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/renesas/common/io/io_rcar.c b/drivers/renesas/common/io/io_rcar.c index c3e8319de..17d7aaa29 100644 --- a/drivers/renesas/common/io/io_rcar.c +++ b/drivers/renesas/common/io/io_rcar.c @@ -151,6 +151,9 @@ int32_t rcar_get_certificate(const int32_t name, uint32_t *cert) return -EINVAL; } +#define MFISBTSTSR (0xE6260604U) +#define MFISBTSTSR_BOOT_PARTITION (0x00000010U) + static int32_t file_to_offset(const int32_t name, uintptr_t *offset, uint32_t *cert, uint32_t *no_load, uintptr_t *partition) @@ -169,6 +172,9 @@ static int32_t file_to_offset(const int32_t name, uintptr_t *offset, } *offset = rcar_image_header[addr]; + + if (mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) + *offset += 0x800000; *cert = RCAR_CERT_SIZE; *cert *= RCAR_ATTR_GET_CERTOFF(name_offset[i].attr); *cert += RCAR_SDRAM_certESS; From 899108601a0c3b08ead5e686d92ea0794700ff35 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Mar 2021 01:22:58 +0100 Subject: [PATCH 18/18] feat(plat/rcar3): keep RWDT enabled In case the WDT is enabled by prior stage, keep it enabled. Signed-off-by: Marek Vasut Change-Id: Ie7c0eaf2f59dd8c30a9ef686a7000424f38d6352 --- plat/renesas/common/bl2_cpg_init.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/renesas/common/bl2_cpg_init.c b/plat/renesas/common/bl2_cpg_init.c index a6579ebcd..a545f7106 100644 --- a/plat/renesas/common/bl2_cpg_init.c +++ b/plat/renesas/common/bl2_cpg_init.c @@ -139,7 +139,7 @@ static void bl2_system_cpg_init_h3(void) cpg_write(SMSTPCR1, 0xFFFFFFFFU); cpg_write(SMSTPCR2, 0x040E2FDCU); cpg_write(SMSTPCR3, 0xFFFFFBDFU); - cpg_write(SMSTPCR4, 0x80000004U); + cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4)); cpg_write(SMSTPCR5, 0xC3FFFFFFU); cpg_write(SMSTPCR6, 0xFFFFFFFFU); cpg_write(SMSTPCR7, 0xFFFFFFFFU); @@ -175,7 +175,7 @@ static void bl2_system_cpg_init_m3(void) cpg_write(SMSTPCR1, 0xFFFFFFFFU); cpg_write(SMSTPCR2, 0x040E2FDCU); cpg_write(SMSTPCR3, 0xFFFFFBDFU); - cpg_write(SMSTPCR4, 0x80000004U); + cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4)); cpg_write(SMSTPCR5, 0xC3FFFFFFU); cpg_write(SMSTPCR6, 0xFFFFFFFFU); cpg_write(SMSTPCR7, 0xFFFFFFFFU); @@ -211,7 +211,7 @@ static void bl2_system_cpg_init_m3n(void) cpg_write(SMSTPCR1, 0xFFFFFFFFU); cpg_write(SMSTPCR2, 0x040E2FDCU); cpg_write(SMSTPCR3, 0xFFFFFBDFU); - cpg_write(SMSTPCR4, 0x80000004U); + cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4)); cpg_write(SMSTPCR5, 0xC3FFFFFFU); cpg_write(SMSTPCR6, 0xFFFFFFFFU); cpg_write(SMSTPCR7, 0xFFFFFFFFU); @@ -245,7 +245,7 @@ static void bl2_system_cpg_init_v3m(void) cpg_write(SMSTPCR1, 0xFFFFFFFFU); cpg_write(SMSTPCR2, 0x340E2FDCU); cpg_write(SMSTPCR3, 0xFFFFFBDFU); - cpg_write(SMSTPCR4, 0x80000004U); + cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4)); cpg_write(SMSTPCR5, 0xC3FFFFFFU); cpg_write(SMSTPCR6, 0xFFFFFFFFU); cpg_write(SMSTPCR7, 0xFFFFFFFFU); @@ -279,7 +279,7 @@ static void bl2_system_cpg_init_e3(void) cpg_write(SMSTPCR1, 0xFFFFFFFFU); cpg_write(SMSTPCR2, 0x000E2FDCU); cpg_write(SMSTPCR3, 0xFFFFFBDFU); - cpg_write(SMSTPCR4, 0x80000004U); + cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4)); cpg_write(SMSTPCR5, 0xC3FFFFFFU); cpg_write(SMSTPCR6, 0xFFFFFFFFU); cpg_write(SMSTPCR7, 0xFFFFFFFFU); @@ -298,7 +298,7 @@ static void bl2_system_cpg_init_d3(void) cpg_write(SMSTPCR1, 0xFFFFFFFFU); cpg_write(SMSTPCR2, 0x00060FDCU); cpg_write(SMSTPCR3, 0xFFFFFBDFU); - cpg_write(SMSTPCR4, 0x00000084U); + cpg_write(SMSTPCR4, 0x00000080U | (mmio_read_32(SMSTPCR4) & 0x4)); cpg_write(SMSTPCR5, 0x83FFFFFFU); cpg_write(SMSTPCR6, 0xFFFFFFFFU); cpg_write(SMSTPCR7, 0xFFFFFFFFU);