From a727d59d9c1ef5ecf2f221ce289506da2011dda1 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Wed, 20 Sep 2023 23:25:32 +0800 Subject: [PATCH] feat(cpufeat): add cortex-a35 l2 extended control register Add Cortex-A35 l2 extended control register definition. Signed-off-by: Jacky Bai Change-Id: I14c766a88c95fef0f95a6f2e9d8ca87dbeac77c2 --- include/lib/cpus/aarch64/cortex_a35.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h index cef2960d5..c82b4eb03 100644 --- a/include/lib/cpus/aarch64/cortex_a35.h +++ b/include/lib/cpus/aarch64/cortex_a35.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,9 @@ /* Cortex-A35 Main ID register for revision 0 */ #define CORTEX_A35_MIDR U(0x410FD040) +/* L2 Extended Control Register */ +#define CORTEX_A35_L2ECTLR_EL1 S3_1_C11_C0_3 + /******************************************************************************* * CPU Extended Control register specific definitions. * CPUECTLR_EL1 is an implementation-specific register.