Browse Source
* changes: feat(docs/nxp/layerscape): add ls1028a soc and board support feat(plat/nxp/ls1028ardb): add ls1028ardb board support feat(plat/nxp/ls1028a): add ls1028a soc support feat(plat/nxp/common): define default SD buffer feat(driver/nxp/xspi): add MT35XU02G flash info feat(plat/nxp/common): add SecMon register definition for ch_3_2 feat(driver/nxp/dcfg): define RSTCR_RESET_REQ feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS feat(plat/nxp/common): define default PSCI features if not defined feat(plat/nxp/common): define common macro for ARM registers feat(plat/nxp/common): add CCI and EPU address definitionpull/1981/head
Joanna Farley
3 years ago
committed by
TrustedFirmware Code Review
TrustedFirmware Code Review
21 changed files with 2754 additions and 31 deletions
File diff suppressed because it is too large
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/* |
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* Copyright 2018-2021 NXP |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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|
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#include <arch.h> |
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#include <asm_macros.S> |
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|
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#include <platform_def.h> |
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|
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.globl plat_secondary_cold_boot_setup |
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.globl plat_is_my_cpu_primary |
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.globl plat_reset_handler |
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.globl platform_mem_init |
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|
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func platform_mem1_init |
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ret |
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endfunc platform_mem1_init |
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|
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func platform_mem_init |
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ret |
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endfunc platform_mem_init |
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|
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func apply_platform_errata |
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ret |
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endfunc apply_platform_errata |
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|
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func plat_reset_handler |
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mov x29, x30 |
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bl apply_platform_errata |
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|
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#if defined(IMAGE_BL31) |
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ldr x0, =POLICY_SMMU_PAGESZ_64K |
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cbz x0, 1f |
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/* Set the SMMU page size in the sACR register */ |
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bl _set_smmu_pagesz_64 |
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#endif |
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1: |
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mov x30, x29 |
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ret |
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endfunc plat_reset_handler |
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|
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/* |
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* void plat_secondary_cold_boot_setup (void); |
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* |
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* This function performs any platform specific actions |
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* needed for a secondary cpu after a cold reset e.g |
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* mark the cpu's presence, mechanism to place it in a |
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* holding pen etc. |
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*/ |
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func plat_secondary_cold_boot_setup |
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/* ls1028a does not do cold boot for secondary CPU */ |
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cb_panic: |
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b cb_panic |
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endfunc plat_secondary_cold_boot_setup |
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|
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/* |
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* unsigned int plat_is_my_cpu_primary (void); |
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* |
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* Find out whether the current cpu is the primary |
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* cpu. |
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*/ |
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func plat_is_my_cpu_primary |
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mrs x0, mpidr_el1 |
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
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cmp x0, 0x0 |
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cset w0, eq |
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ret |
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endfunc plat_is_my_cpu_primary |
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@ -0,0 +1,149 @@ |
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/*
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* Copyright 2018-2021 NXP |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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|
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#ifndef SOC_H |
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#define SOC_H |
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|
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/* Chassis specific defines - common across SoC's of a particular platform */ |
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#include <dcfg_lsch3.h> |
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#include <soc_default_base_addr.h> |
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#include <soc_default_helper_macros.h> |
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|
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/*
|
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* SVR Definition of LS1028A |
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* (not include major and minor rev) |
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* These info is listed in Table B-6. DCFG differences |
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* between LS1028A and LS1027A of LS1028ARM(Reference Manual) |
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*/ |
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#define SVR_LS1017AN 0x870B25 |
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#define SVR_LS1017AE 0x870B24 |
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#define SVR_LS1018AN 0x870B21 |
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#define SVR_LS1018AE 0x870B20 |
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#define SVR_LS1027AN 0x870B05 |
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#define SVR_LS1027AE 0x870B04 |
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#define SVR_LS1028AN 0x870B01 |
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#define SVR_LS1028AE 0x870B00 |
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|
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/* Number of cores in platform */ |
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#define PLATFORM_CORE_COUNT 2 |
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#define NUMBER_OF_CLUSTERS 1 |
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#define CORES_PER_CLUSTER 2 |
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|
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/* Set to 0 if the clusters are not symmetrical */ |
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#define SYMMETRICAL_CLUSTERS 1 |
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|
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#define NUM_DRAM_REGIONS 3 |
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|
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#define NXP_DRAM0_ADDR 0x80000000 |
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#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2GB */ |
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|
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#define NXP_DRAM1_ADDR 0x2080000000 |
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#define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126G */ |
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|
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#define NXP_DRAM2_ADDR 0x6000000000 |
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#define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */ |
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|
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/* DRAM0 Size defined in platform_def.h */ |
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE |
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|
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/* CCSR space memory Map */ |
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#undef NXP_UART_ADDR |
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#define NXP_UART_ADDR 0x021C0500 |
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|
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#undef NXP_UART1_ADDR |
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#define NXP_UART1_ADDR 0x021C0600 |
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#undef NXP_WDOG1_TZ_ADDR |
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#define NXP_WDOG1_TZ_ADDR 0x023C0000 |
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#undef NXP_GICR_ADDR |
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#define NXP_GICR_ADDR 0x06040000 |
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|
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#undef NXP_GICR_SGI_ADDR |
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#define NXP_GICR_SGI_ADDR 0x06050000 |
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|
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/* EPU register offsets and values */ |
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#define EPU_EPGCR_OFFSET 0x0 |
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#define EPU_EPIMCR10_OFFSET 0x128 |
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#define EPU_EPCTR10_OFFSET 0xa28 |
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#define EPU_EPCCR10_OFFSET 0x828 |
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#define EPU_EPCCR10_VAL 0xb2800000 |
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#define EPU_EPIMCR10_VAL 0xba000000 |
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#define EPU_EPCTR10_VAL 0x0 |
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#define EPU_EPGCR_VAL (1 << 31) |
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|
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/* PORSR1 */ |
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#define PORSR1_RCW_MASK 0x07800000 |
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#define PORSR1_RCW_SHIFT 23 |
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|
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#define SDHC1_VAL 0x8 |
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#define SDHC2_VAL 0x9 |
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#define I2C1_VAL 0xa |
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#define FLEXSPI_NAND2K_VAL 0xc |
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#define FLEXSPI_NAND4K_VAL 0xd |
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#define FLEXSPI_NOR 0xf |
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|
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/*
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* Required LS standard platform porting definitions |
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* for CCI-400 |
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*/ |
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#define NXP_CCI_CLUSTER0_SL_IFACE_IX 4 |
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|
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/* Defines required for using XLAT tables from ARM common code */ |
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40) |
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40) |
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|
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/* Clock Divisors */ |
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#define NXP_PLATFORM_CLK_DIVIDER 1 |
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#define NXP_UART_CLK_DIVIDER 2 |
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|
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/* dcfg register offsets and values */ |
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#define DCFG_DEVDISR2_ENETC (1 << 31) |
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|
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#define MPIDR_AFFINITY0_MASK 0x00FF |
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#define MPIDR_AFFINITY1_MASK 0xFF00 |
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#define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000 |
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#define CPUECTLR_INS_PREFETCH_MASK 0x1800000000 |
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#define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000 |
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#define OSDLR_EL1_DLK_LOCK 0x1 |
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#define CNTP_CTL_EL0_EN 0x1 |
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#define CNTP_CTL_EL0_IMASK 0x2 |
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|
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#define SYSTEM_PWR_DOMAINS 1 |
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ |
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NUMBER_OF_CLUSTERS + \ |
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SYSTEM_PWR_DOMAINS) |
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|
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/* Power state coordination occurs at the system level */ |
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#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2 |
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#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL |
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|
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/* Local power state for power domains in Run state */ |
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#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN |
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|
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/* define retention state */ |
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) |
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#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE |
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|
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/* define power-down state */ |
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) |
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#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE |
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|
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/* One cache line needed for bakery locks on ARM platforms */ |
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) |
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|
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#ifndef __ASSEMBLER__ |
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/* CCI slave interfaces */ |
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static const int cci_map[] = { |
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NXP_CCI_CLUSTER0_SL_IFACE_IX, |
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}; |
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void soc_init_lowlevel(void); |
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void soc_init_percpu(void); |
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void _soc_set_start_addr(unsigned long addr); |
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void _set_platform_security(void); |
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#endif |
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|
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#endif /* SOC_H */ |
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@ -0,0 +1,185 @@ |
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/*
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* Copyright 2018-2021 NXP |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <string.h> |
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|
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#include <common/debug.h> |
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#include <ddr.h> |
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#include <lib/utils.h> |
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|
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#include <platform_def.h> |
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|
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#ifdef CONFIG_STATIC_DDR |
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const struct ddr_cfg_regs static_1600 = { |
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.cs[0].config = U(0x80040422), |
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.cs[0].bnds = U(0xFF), |
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.sdram_cfg[0] = U(0xE50C0004), |
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.sdram_cfg[1] = U(0x401100), |
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.timing_cfg[0] = U(0x91550018), |
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.timing_cfg[1] = U(0xBAB40C42), |
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.timing_cfg[2] = U(0x48C111), |
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.timing_cfg[3] = U(0x1111000), |
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.timing_cfg[4] = U(0x2), |
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.timing_cfg[5] = U(0x3401400), |
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.timing_cfg[7] = U(0x23300000), |
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.timing_cfg[8] = U(0x2114600), |
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.sdram_mode[0] = U(0x3010210), |
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.sdram_mode[9] = U(0x4000000), |
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.sdram_mode[8] = U(0x500), |
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.sdram_mode[2] = U(0x10210), |
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.sdram_mode[10] = U(0x400), |
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.sdram_mode[11] = U(0x4000000), |
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.sdram_mode[4] = U(0x10210), |
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.sdram_mode[12] = U(0x400), |
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.sdram_mode[13] = U(0x4000000), |
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.sdram_mode[6] = U(0x10210), |
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.sdram_mode[14] = U(0x400), |
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.sdram_mode[15] = U(0x4000000), |
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.interval = U(0x18600618), |
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.data_init = U(0xdeadbeef), |
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.zq_cntl = U(0x8A090705), |
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.clk_cntl = U(0x2000000), |
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.cdr[0] = U(0x80040000), |
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.cdr[1] = U(0xA181), |
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.wrlvl_cntl[0] = U(0x8675F605), |
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.wrlvl_cntl[1] = U(0x6070700), |
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.wrlvl_cntl[2] = U(0x0000008), |
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.dq_map[0] = U(0x5b65b658), |
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.dq_map[1] = U(0xd96d8000), |
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.dq_map[2] = U(0), |
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.dq_map[3] = U(0x1600000), |
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.debug[28] = U(0x00700046), |
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}; |
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|
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unsigned long long board_static_ddr(struct ddr_info *priv) |
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{ |
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memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600)); |
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return ULL(0x100000000); |
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} |
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#else |
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static const struct rc_timing rcz[] = { |
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{1600, 8, 5}, |
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{} |
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}; |
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static const struct board_timing ram[] = { |
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{0x1f, rcz, 0x1020200, 0x00000003}, |
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}; |
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int ddr_board_options(struct ddr_info *priv) |
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{ |
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int ret; |
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struct memctl_opt *popts = &priv->opt; |
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ret = cal_board_params(priv, ram, ARRAY_SIZE(ram)); |
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if (ret != 0) { |
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return ret; |
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} |
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popts->bstopre = U(0x40); /* precharge value */ |
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popts->half_strength_drive_en = 1; |
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popts->cpo_sample = U(0x46); |
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | |
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DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); |
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | |
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DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ |
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popts->addr_hash = 1; /* address hashing */ |
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return 0; |
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} |
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/* DDR model number: MT40A1G8SA-075:E */ |
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struct dimm_params ddr_raw_timing = { |
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.n_ranks = U(1), |
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.rank_density = ULL(4294967296), |
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.capacity = ULL(4294967296), |
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.primary_sdram_width = U(32), |
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.ec_sdram_width = U(4), |
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.rdimm = U(0), |
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.mirrored_dimm = U(0), |
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.n_row_addr = U(16), |
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.n_col_addr = U(10), |
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.bank_group_bits = U(2), |
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.edc_config = U(2), |
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.burst_lengths_bitmask = U(0x0c), |
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.tckmin_x_ps = 750, |
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.tckmax_ps = 1900, |
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.caslat_x = U(0x0001FFE00), |
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.taa_ps = 13500, |
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.trcd_ps = 13500, |
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.trp_ps = 13500, |
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.tras_ps = 32000, |
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.trc_ps = 45500, |
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.twr_ps = 15000, |
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.trfc1_ps = 350000, |
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.trfc2_ps = 260000, |
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.trfc4_ps = 160000, |
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.tfaw_ps = 21000, |
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.trrds_ps = 3000, |
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.trrdl_ps = 4900, |
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.tccdl_ps = 5000, |
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.refresh_rate_ps = U(7800000), |
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.dq_mapping[0] = U(0x16), |
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.dq_mapping[1] = U(0x36), |
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.dq_mapping[2] = U(0x16), |
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.dq_mapping[3] = U(0x36), |
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.dq_mapping[4] = U(0x16), |
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.dq_mapping[5] = U(0x36), |
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.dq_mapping[6] = U(0x16), |
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.dq_mapping[7] = U(0x36), |
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.dq_mapping[8] = U(0x16), |
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.dq_mapping[9] = U(0x0), |
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.dq_mapping[10] = U(0x0), |
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.dq_mapping[11] = U(0x0), |
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.dq_mapping[12] = U(0x0), |
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.dq_mapping[13] = U(0x0), |
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.dq_mapping[14] = U(0x0), |
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.dq_mapping[15] = U(0x0), |
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.dq_mapping[16] = U(0x0), |
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.dq_mapping[17] = U(0x0), |
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.dq_mapping_ors = U(0), |
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.rc = U(0x1f), |
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}; |
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|
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int ddr_get_ddr_params(struct dimm_params *pdimm, |
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struct ddr_conf *conf) |
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{ |
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static const char dimm_model[] = "Fixed DDR on board"; |
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conf->dimm_in_use[0] = 1; |
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memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params)); |
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); |
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return 1; |
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} |
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#endif |
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|
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int64_t init_ddr(void) |
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{ |
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struct ddr_info info; |
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struct sysinfo sys; |
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int64_t dram_size; |
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|
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zeromem(&sys, sizeof(sys)); |
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get_clocks(&sys); |
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debug("platform clock %lu\n", sys.freq_platform); |
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debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); |
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|
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zeromem(&info, sizeof(struct ddr_info)); |
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info.num_ctlrs = 1; |
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info.dimm_on_ctlr = 1; |
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info.clk = get_ddr_freq(&sys, 0); |
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info.ddr[0] = (void *)NXP_DDR_ADDR; |
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|
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dram_size = dram_init(&info); |
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|
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if (dram_size < 0) { |
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ERROR("DDR init failed.\n"); |
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} |
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|
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return dram_size; |
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} |
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@ -0,0 +1,76 @@ |
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/*
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* Copyright 2018-2021 NXP |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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|
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#ifndef PLAT_DEF_H |
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#define PLAT_DEF_H |
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|
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#include <arch.h> |
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#include <cortex_a72.h> |
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/*
|
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* Required without TBBR. |
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* To include the defines for DDR PHY |
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* Images. |
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*/ |
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#include <tbbr_img_def.h> |
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|
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#include <policy.h> |
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#include <soc.h> |
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|
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|
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#define NXP_SYSCLK_FREQ 100000000 |
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#define NXP_DDRCLK_FREQ 100000000 |
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|
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/* UART related definition */ |
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#define NXP_CONSOLE_ADDR NXP_UART_ADDR |
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#define NXP_CONSOLE_BAUDRATE 115200 |
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|
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#define NXP_SPD_EEPROM0 0x51 |
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|
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/* Size of cacheable stacks */ |
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#if defined(IMAGE_BL2) |
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#if defined(TRUSTED_BOARD_BOOT) |
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#define PLATFORM_STACK_SIZE 0x2000 |
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#else |
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#define PLATFORM_STACK_SIZE 0x1000 |
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#endif |
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#elif defined(IMAGE_BL31) |
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#define PLATFORM_STACK_SIZE 0x1000 |
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#endif |
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|
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/* SD block buffer */ |
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#define NXP_SD_BLOCK_BUF_SIZE (0xC000) |
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|
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#ifdef SD_BOOT |
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#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ |
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- NXP_SD_BLOCK_BUF_SIZE) |
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#else |
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#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) |
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#endif |
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#define BL2_TEXT_LIMIT (BL2_LIMIT) |
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|
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/* IO defines as needed by IO driver framework */ |
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#define MAX_IO_DEVICES 4 |
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#define MAX_IO_BLOCK_DEVICES 1 |
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#define MAX_IO_HANDLES 4 |
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#define BL31_WDOG_SEC 89 |
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|
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 |
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* terminology. On a GICv2 system or mode, the lists will be merged and treated |
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* as Group 0 interrupts. |
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*/ |
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#define PLAT_LS_G1S_IRQ_PROPS(grp) \ |
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INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
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GIC_INTR_CFG_EDGE) |
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|
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/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ |
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#define PLAT_LS_G0_IRQ_PROPS(grp) \ |
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INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
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GIC_INTR_CFG_EDGE), \ |
|||
INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
|||
GIC_INTR_CFG_LEVEL) |
|||
#endif /* PLAT_DEF_H */ |
|||
@ -0,0 +1,28 @@ |
|||
/*
|
|||
* Copyright 2020-2021 NXP |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#include <plat_common.h> |
|||
|
|||
#pragma weak board_enable_povdd |
|||
#pragma weak board_disable_povdd |
|||
|
|||
bool board_enable_povdd(void) |
|||
{ |
|||
#ifdef CONFIG_POVDD_ENABLE |
|||
return true; |
|||
#else |
|||
return false; |
|||
#endif |
|||
} |
|||
|
|||
bool board_disable_povdd(void) |
|||
{ |
|||
#ifdef CONFIG_POVDD_ENABLE |
|||
return true; |
|||
#else |
|||
return false; |
|||
#endif |
|||
} |
|||
@ -0,0 +1,33 @@ |
|||
#
|
|||
# Copyright 2020-2021 NXP
|
|||
#
|
|||
# SPDX-License-Identifier: BSD-3-Clause
|
|||
#
|
|||
|
|||
# Board-specific build parameters
|
|||
BOOT_MODE ?= flexspi_nor |
|||
BOARD := ls1028ardb |
|||
POVDD_ENABLE := no |
|||
WARM_BOOT := no |
|||
|
|||
# DDR build parameters
|
|||
NUM_OF_DDRC := 1 |
|||
CONFIG_DDR_NODIMM := 1 |
|||
DDR_ECC_EN := yes |
|||
|
|||
# On-board flash
|
|||
FLASH_TYPE := MT35XU02G |
|||
XSPI_FLASH_SZ := 0x10000000 |
|||
|
|||
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c \
|
|||
${BOARD_PATH}/platform.c |
|||
|
|||
SUPPORTED_BOOT_MODE := flexspi_nor \
|
|||
sd \
|
|||
emmc |
|||
|
|||
# Add platform board build info
|
|||
include plat/nxp/common/plat_make_helper/plat_common_def.mk |
|||
|
|||
# Add SoC build info
|
|||
include plat/nxp/soc-ls1028a/soc.mk |
|||
@ -0,0 +1,13 @@ |
|||
/*
|
|||
* Copyright 2021 NXP |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#ifndef PLATFORM_DEF_H |
|||
#define PLATFORM_DEF_H |
|||
|
|||
#include <plat_def.h> |
|||
#include <plat_default_def.h> |
|||
|
|||
#endif /* PLATFORM_DEF_H */ |
|||
@ -0,0 +1,16 @@ |
|||
/*
|
|||
* Copyright 2020-2021 NXP |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#ifndef POLICY_H |
|||
#define POLICY_H |
|||
|
|||
/*
|
|||
* Set this to 0x0 to leave the default SMMU page size in sACR |
|||
* Set this to 0x1 to change the SMMU page size to 64K |
|||
*/ |
|||
#define POLICY_SMMU_PAGESZ_64K 0x1 |
|||
|
|||
#endif /* POLICY_H */ |
|||
@ -0,0 +1,420 @@ |
|||
/*
|
|||
* Copyright 2018-2021 NXP |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#include <endian.h> |
|||
|
|||
#include <arch.h> |
|||
#include <caam.h> |
|||
#include <cassert.h> |
|||
#include <cci.h> |
|||
#include <common/debug.h> |
|||
#include <dcfg.h> |
|||
#include <i2c.h> |
|||
#include <lib/xlat_tables/xlat_tables_v2.h> |
|||
#include <ls_interconnect.h> |
|||
#include <mmio.h> |
|||
#if TRUSTED_BOARD_BOOT |
|||
#include <nxp_smmu.h> |
|||
#endif |
|||
#include <nxp_timer.h> |
|||
#ifdef CONFIG_OCRAM_ECC_EN |
|||
#include <ocram.h> |
|||
#endif |
|||
#include <plat_console.h> |
|||
#include <plat_gic.h> |
|||
#include <plat_tzc400.h> |
|||
#include <pmu.h> |
|||
#include <scfg.h> |
|||
#if defined(NXP_SFP_ENABLED) |
|||
#include <sfp.h> |
|||
#endif |
|||
|
|||
#include <errata.h> |
|||
#include "plat_common.h" |
|||
#include "platform_def.h" |
|||
#include "soc.h" |
|||
|
|||
static dcfg_init_info_t dcfg_init_data = { |
|||
.g_nxp_dcfg_addr = NXP_DCFG_ADDR, |
|||
.nxp_sysclk_freq = NXP_SYSCLK_FREQ, |
|||
.nxp_ddrclk_freq = NXP_DDRCLK_FREQ, |
|||
.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, |
|||
}; |
|||
|
|||
static struct soc_type soc_list[] = { |
|||
SOC_ENTRY(LS1017AN, LS1017AN, 1, 1), |
|||
SOC_ENTRY(LS1017AE, LS1017AE, 1, 1), |
|||
SOC_ENTRY(LS1018AN, LS1018AN, 1, 1), |
|||
SOC_ENTRY(LS1018AE, LS1018AE, 1, 1), |
|||
SOC_ENTRY(LS1027AN, LS1027AN, 1, 2), |
|||
SOC_ENTRY(LS1027AE, LS1027AE, 1, 2), |
|||
SOC_ENTRY(LS1028AN, LS1028AN, 1, 2), |
|||
SOC_ENTRY(LS1028AE, LS1028AE, 1, 2), |
|||
}; |
|||
|
|||
CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, |
|||
assert_invalid_ls1028a_cluster_count); |
|||
|
|||
/*
|
|||
* Function returns the base counter frequency |
|||
* after reading the first entry at CNTFID0 (0x20 offset). |
|||
* |
|||
* Function is used by: |
|||
* 1. ARM common code for PSCI management. |
|||
* 2. ARM Generic Timer init. |
|||
* |
|||
*/ |
|||
unsigned int plat_get_syscnt_freq2(void) |
|||
{ |
|||
unsigned int counter_base_frequency; |
|||
/*
|
|||
* Below register specifies the base frequency of the system counter. |
|||
* As per NXP Board Manuals: |
|||
* The system counter always works with SYS_REF_CLK/4 frequency clock. |
|||
*/ |
|||
counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); |
|||
|
|||
return counter_base_frequency; |
|||
} |
|||
|
|||
#ifdef IMAGE_BL2 |
|||
void soc_preload_setup(void) |
|||
{ |
|||
} |
|||
|
|||
void soc_early_init(void) |
|||
{ |
|||
uint8_t num_clusters, cores_per_cluster; |
|||
|
|||
#ifdef CONFIG_OCRAM_ECC_EN |
|||
ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); |
|||
#endif |
|||
dcfg_init(&dcfg_init_data); |
|||
enable_timer_base_to_cluster(NXP_PMU_ADDR); |
|||
enable_core_tb(NXP_PMU_ADDR); |
|||
dram_regions_info_t *dram_regions_info = get_dram_regions_info(); |
|||
|
|||
#ifdef POLICY_FUSE_PROVISION |
|||
gpio_init(&gpio_init_data); |
|||
sec_init(NXP_CAAM_ADDR); |
|||
#endif |
|||
|
|||
#if LOG_LEVEL > 0 |
|||
/* Initialize the console to provide early debug support */ |
|||
plat_console_init(NXP_CONSOLE_ADDR, |
|||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); |
|||
#endif |
|||
enum boot_device dev = get_boot_dev(); |
|||
/*
|
|||
* Mark the buffer for SD in OCRAM as non secure. |
|||
* The buffer is assumed to be at end of OCRAM for |
|||
* the logic below to calculate TZPC programming |
|||
*/ |
|||
if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) { |
|||
/*
|
|||
* Calculate the region in OCRAM which is secure |
|||
* The buffer for SD needs to be marked non-secure |
|||
* to allow SD to do DMA operations on it |
|||
*/ |
|||
uint32_t secure_region = (NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE); |
|||
uint32_t mask = secure_region/TZPC_BLOCK_SIZE; |
|||
|
|||
mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask); |
|||
|
|||
/* Add the entry for buffer in MMU Table */ |
|||
mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, |
|||
NXP_SD_BLOCK_BUF_SIZE, MT_DEVICE | MT_RW | MT_NS); |
|||
} |
|||
|
|||
#if TRUSTED_BOARD_BOOT |
|||
uint32_t mode; |
|||
|
|||
sfp_init(NXP_SFP_ADDR); |
|||
|
|||
/*
|
|||
* For secure boot disable SMMU. |
|||
* Later when platform security policy comes in picture, |
|||
* this might get modified based on the policy |
|||
*/ |
|||
if (check_boot_mode_secure(&mode) == true) { |
|||
bypass_smmu(NXP_SMMU_ADDR); |
|||
} |
|||
|
|||
/*
|
|||
* For Mbedtls currently crypto is not supported via CAAM |
|||
* enable it when that support is there. In tbbr.mk |
|||
* the CAAM_INTEG is set as 0. |
|||
*/ |
|||
#ifndef MBEDTLS_X509 |
|||
/* Initialize the crypto accelerator if enabled */ |
|||
if (is_sec_enabled()) { |
|||
sec_init(NXP_CAAM_ADDR); |
|||
} else { |
|||
INFO("SEC is disabled.\n"); |
|||
} |
|||
#endif |
|||
#endif |
|||
|
|||
/* Set eDDRTQ for DDR performance */ |
|||
scfg_setbits32((void *)(NXP_SCFG_ADDR + 0x210), 0x1f1f1f1f); |
|||
|
|||
soc_errata(); |
|||
|
|||
/*
|
|||
* Initialize Interconnect for this cluster during cold boot. |
|||
* No need for locks as no other CPU is active. |
|||
*/ |
|||
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); |
|||
|
|||
/*
|
|||
* Enable Interconnect coherency for the primary CPU's cluster. |
|||
*/ |
|||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); |
|||
plat_ls_interconnect_enter_coherency(num_clusters); |
|||
|
|||
delay_timer_init(NXP_TIMER_ADDR); |
|||
i2c_init(NXP_I2C_ADDR); |
|||
dram_regions_info->total_dram_size = init_ddr(); |
|||
} |
|||
|
|||
void soc_bl2_prepare_exit(void) |
|||
{ |
|||
#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) |
|||
set_sfp_wr_disable(); |
|||
#endif |
|||
} |
|||
|
|||
/*
|
|||
* This function returns the boot device based on RCW_SRC |
|||
*/ |
|||
enum boot_device get_boot_dev(void) |
|||
{ |
|||
enum boot_device src = BOOT_DEVICE_NONE; |
|||
uint32_t porsr1; |
|||
uint32_t rcw_src; |
|||
|
|||
porsr1 = read_reg_porsr1(); |
|||
|
|||
rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; |
|||
switch (rcw_src) { |
|||
case FLEXSPI_NOR: |
|||
src = BOOT_DEVICE_FLEXSPI_NOR; |
|||
INFO("RCW BOOT SRC is FLEXSPI NOR\n"); |
|||
break; |
|||
case FLEXSPI_NAND2K_VAL: |
|||
case FLEXSPI_NAND4K_VAL: |
|||
INFO("RCW BOOT SRC is FLEXSPI NAND\n"); |
|||
src = BOOT_DEVICE_FLEXSPI_NAND; |
|||
break; |
|||
case SDHC1_VAL: |
|||
src = BOOT_DEVICE_EMMC; |
|||
INFO("RCW BOOT SRC is SD\n"); |
|||
break; |
|||
case SDHC2_VAL: |
|||
src = BOOT_DEVICE_SDHC2_EMMC; |
|||
INFO("RCW BOOT SRC is EMMC\n"); |
|||
break; |
|||
default: |
|||
break; |
|||
} |
|||
|
|||
return src; |
|||
} |
|||
|
|||
/*
|
|||
* This function sets up access permissions on memory regions |
|||
****************************************************************************/ |
|||
void soc_mem_access(void) |
|||
{ |
|||
dram_regions_info_t *info_dram_regions = get_dram_regions_info(); |
|||
struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; |
|||
int dram_idx = 0; |
|||
/* index 0 is reserved for region-0 */ |
|||
int index = 1; |
|||
|
|||
for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions; |
|||
dram_idx++) { |
|||
if (info_dram_regions->region[dram_idx].size == 0) { |
|||
ERROR("DDR init failure, or"); |
|||
ERROR("DRAM regions not populated correctly.\n"); |
|||
break; |
|||
} |
|||
|
|||
index = populate_tzc400_reg_list(tzc400_reg_list, |
|||
dram_idx, index, |
|||
info_dram_regions->region[dram_idx].addr, |
|||
info_dram_regions->region[dram_idx].size, |
|||
NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); |
|||
} |
|||
|
|||
mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list); |
|||
} |
|||
|
|||
#else |
|||
|
|||
static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2]; |
|||
/*
|
|||
* This function dynamically constructs the topology according to |
|||
* SoC Flavor and returns it. |
|||
*/ |
|||
const unsigned char *plat_get_power_domain_tree_desc(void) |
|||
{ |
|||
uint8_t num_clusters, cores_per_cluster; |
|||
unsigned int i; |
|||
|
|||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); |
|||
/*
|
|||
* The highest level is the system level. The next level is constituted |
|||
* by clusters and then cores in clusters. |
|||
*/ |
|||
_power_domain_tree_desc[0] = 1; |
|||
_power_domain_tree_desc[1] = num_clusters; |
|||
|
|||
for (i = 0; i < _power_domain_tree_desc[1]; i++) |
|||
_power_domain_tree_desc[i + 2] = cores_per_cluster; |
|||
|
|||
return _power_domain_tree_desc; |
|||
} |
|||
|
|||
/*
|
|||
* This function returns the core count within the cluster corresponding to |
|||
* `mpidr`. |
|||
*/ |
|||
unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) |
|||
{ |
|||
uint8_t num_clusters, cores_per_cluster; |
|||
|
|||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); |
|||
return num_clusters; |
|||
} |
|||
|
|||
void soc_early_platform_setup2(void) |
|||
{ |
|||
dcfg_init(&dcfg_init_data); |
|||
/* Initialize system level generic timer for Socs */ |
|||
delay_timer_init(NXP_TIMER_ADDR); |
|||
|
|||
#if LOG_LEVEL > 0 |
|||
/* Initialize the console to provide early debug support */ |
|||
plat_console_init(NXP_CONSOLE_ADDR, |
|||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); |
|||
#endif |
|||
} |
|||
|
|||
void soc_platform_setup(void) |
|||
{ |
|||
/* Initialize the GIC driver, cpu and distributor interfaces */ |
|||
static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; |
|||
static interrupt_prop_t ls_interrupt_props[] = { |
|||
PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), |
|||
PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) |
|||
}; |
|||
|
|||
plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, |
|||
PLATFORM_CORE_COUNT, |
|||
ls_interrupt_props, |
|||
ARRAY_SIZE(ls_interrupt_props), |
|||
target_mask_array, |
|||
plat_core_pos); |
|||
|
|||
plat_ls_gic_init(); |
|||
enable_init_timer(); |
|||
} |
|||
|
|||
/* This function initializes the soc from the BL31 module */ |
|||
void soc_init(void) |
|||
{ |
|||
uint8_t num_clusters, cores_per_cluster; |
|||
|
|||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); |
|||
|
|||
/* Low-level init of the soc */ |
|||
soc_init_lowlevel(); |
|||
_init_global_data(); |
|||
soc_init_percpu(); |
|||
_initialize_psci(); |
|||
|
|||
/*
|
|||
* Initialize Interconnect for this cluster during cold boot. |
|||
* No need for locks as no other CPU is active. |
|||
*/ |
|||
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); |
|||
|
|||
/* Enable Interconnect coherency for the primary CPU's cluster. */ |
|||
plat_ls_interconnect_enter_coherency(num_clusters); |
|||
|
|||
/* Set platform security policies */ |
|||
_set_platform_security(); |
|||
|
|||
/* Init SEC Engine which will be used by SiP */ |
|||
if (is_sec_enabled()) { |
|||
sec_init(NXP_CAAM_ADDR); |
|||
} else { |
|||
INFO("SEC is disabled.\n"); |
|||
} |
|||
} |
|||
|
|||
#ifdef NXP_WDOG_RESTART |
|||
static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, |
|||
void *handle, void *cookie) |
|||
{ |
|||
uint8_t data = WDOG_RESET_FLAG; |
|||
|
|||
wr_nv_app_data(WDT_RESET_FLAG_OFFSET, |
|||
(uint8_t *)&data, sizeof(data)); |
|||
|
|||
mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); |
|||
|
|||
return 0; |
|||
} |
|||
#endif |
|||
|
|||
void soc_runtime_setup(void) |
|||
{ |
|||
#ifdef NXP_WDOG_RESTART |
|||
request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler); |
|||
#endif |
|||
} |
|||
|
|||
/* This function returns the total number of cores in the SoC. */ |
|||
unsigned int get_tot_num_cores(void) |
|||
{ |
|||
uint8_t num_clusters, cores_per_cluster; |
|||
|
|||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); |
|||
return (num_clusters * cores_per_cluster); |
|||
} |
|||
|
|||
/* This function returns the PMU IDLE Cluster mask. */ |
|||
unsigned int get_pmu_idle_cluster_mask(void) |
|||
{ |
|||
uint8_t num_clusters, cores_per_cluster; |
|||
|
|||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); |
|||
return ((1 << num_clusters) - 2); |
|||
} |
|||
|
|||
/* This function returns the PMU Flush Cluster mask. */ |
|||
unsigned int get_pmu_flush_cluster_mask(void) |
|||
{ |
|||
uint8_t num_clusters, cores_per_cluster; |
|||
|
|||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); |
|||
return ((1 << num_clusters) - 2); |
|||
} |
|||
|
|||
/* This function returns the PMU idle core mask. */ |
|||
unsigned int get_pmu_idle_core_mask(void) |
|||
{ |
|||
return ((1 << get_tot_num_cores()) - 2); |
|||
} |
|||
|
|||
/* Function to return the SoC SYS CLK */ |
|||
unsigned int get_sys_clk(void) |
|||
{ |
|||
return NXP_SYSCLK_FREQ; |
|||
} |
|||
#endif |
|||
@ -0,0 +1,95 @@ |
|||
# |
|||
# Copyright 2018-2021 NXP |
|||
# |
|||
# SPDX-License-Identifier: BSD-3-Clause |
|||
# |
|||
# |
|||
#------------------------------------------------------------------------------ |
|||
# |
|||
# This file contains the basic architecture definitions that drive the build |
|||
# |
|||
# ----------------------------------------------------------------------------- |
|||
|
|||
CORE_TYPE := a72 |
|||
|
|||
CACHE_LINE := 6 |
|||
|
|||
# Set to GIC400 or GIC500 |
|||
GIC := GIC500 |
|||
|
|||
# Set to CCI400 or CCN504 or CCN508 |
|||
INTERCONNECT := CCI400 |
|||
|
|||
# Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 |
|||
CHASSIS := 3_2 |
|||
|
|||
# TZC used is TZC380 or TZC400 |
|||
TZC_ID := TZC400 |
|||
|
|||
# CONSOLE is NS16550 or PL011 |
|||
CONSOLE := NS16550 |
|||
|
|||
# DDR PHY generation to be used |
|||
PLAT_DDR_PHY := PHY_GEN1 |
|||
|
|||
PHYS_SYS := 64 |
|||
|
|||
# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def |
|||
# Input to CST create_hdr_esbc tool |
|||
CSF_HDR_SZ := 0x3000 |
|||
|
|||
# In IMAGE_BL2, compile time flag for handling Cache coherency |
|||
# with CAAM for BL2 running from OCRAM |
|||
SEC_MEM_NON_COHERENT := yes |
|||
|
|||
# OCRAM MAP for BL2 |
|||
# Before BL2 |
|||
# 0x18000000 - 0x18009fff -> Used by ROM code |
|||
# 0x1800a000 - 0x1800dfff -> CSF header for BL2 |
|||
# For FlexSFlexSPI boot |
|||
# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary |
|||
# For SD boot |
|||
# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary |
|||
# 0x18030000 - 0x18040000 -> Reserved for SD buffer |
|||
OCRAM_START_ADDR := 0x18000000 |
|||
OCRAM_SIZE := 0x40000 |
|||
|
|||
# Area of OCRAM reserved by ROM code |
|||
NXP_ROM_RSVD := 0xa000 |
|||
|
|||
# Location of BL2 on OCRAM |
|||
BL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) ))) |
|||
|
|||
# Covert to HEX to be used by create_pbl.mk |
|||
BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)) |
|||
|
|||
# BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD) |
|||
# This value BL2_HDR_LOC + CSF_HDR_SZ should not |
|||
# overalp with BL2_BASE |
|||
# Input to CST create_hdr_isbc tool |
|||
BL2_HDR_LOC := 0x1800A000 |
|||
|
|||
# SoC ERRATAS to be enabled |
|||
ERRATA_SOC_A008850 := 1 |
|||
|
|||
ERRATA_DDR_A009803 := 1 |
|||
ERRATA_DDR_A009942 := 1 |
|||
ERRATA_DDR_A010165 := 1 |
|||
|
|||
# Enable dynamic memory mapping |
|||
PLAT_XLAT_TABLES_DYNAMIC := 1 |
|||
|
|||
# Define Endianness of each module |
|||
NXP_GUR_ENDIANNESS := LE |
|||
NXP_DDR_ENDIANNESS := LE |
|||
NXP_SEC_ENDIANNESS := LE |
|||
NXP_SFP_ENDIANNESS := LE |
|||
NXP_SNVS_ENDIANNESS := LE |
|||
NXP_ESDHC_ENDIANNESS := LE |
|||
NXP_QSPI_ENDIANNESS := LE |
|||
NXP_FSPI_ENDIANNESS := LE |
|||
|
|||
NXP_SFP_VER := 3_4 |
|||
|
|||
# OCRAM ECC Enabled |
|||
OCRAM_ECC_EN := yes |
|||
@ -0,0 +1,113 @@ |
|||
#
|
|||
# Copyright 2020-2021 NXP
|
|||
#
|
|||
# SPDX-License-Identifier: BSD-3-Clause
|
|||
#
|
|||
|
|||
# SoC-specific build parameters
|
|||
SOC := ls1028a |
|||
PLAT_PATH := plat/nxp |
|||
PLAT_COMMON_PATH := plat/nxp/common |
|||
PLAT_DRIVERS_PATH := drivers/nxp |
|||
PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC} |
|||
BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD} |
|||
|
|||
# Get SoC-specific definitions
|
|||
include ${PLAT_SOC_PATH}/soc.def |
|||
include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk |
|||
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk |
|||
|
|||
ifeq (${TRUSTED_BOARD_BOOT},1) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) |
|||
SECURE_BOOT := yes |
|||
endif |
|||
$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM)) |
|||
|
|||
$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2)) |
|||
|
|||
# Selecting PSCI & SIP_SVC support
|
|||
$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31)) |
|||
$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31)) |
|||
|
|||
PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
|
|||
-I${BOARD_PATH}\
|
|||
-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
|
|||
-I${PLAT_SOC_PATH}/include\
|
|||
-I${PLAT_COMMON_PATH}/soc_errata |
|||
|
|||
ifeq (${SECURE_BOOT},yes) |
|||
include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk |
|||
endif |
|||
|
|||
ifeq ($(WARM_BOOT),yes) |
|||
include ${PLAT_COMMON_PATH}/warm_reset/warm_reset.mk |
|||
endif |
|||
|
|||
ifeq (${NXP_NV_SW_MAINT_LAST_EXEC_DATA}, yes) |
|||
include ${PLAT_COMMON_PATH}/nv_storage/nv_storage.mk |
|||
endif |
|||
|
|||
ifeq (${PSCI_NEEDED}, yes) |
|||
include ${PLAT_COMMON_PATH}/psci/psci.mk |
|||
endif |
|||
|
|||
ifeq (${SIPSVC_NEEDED}, yes) |
|||
include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk |
|||
endif |
|||
|
|||
ifeq (${DDR_FIP_IO_NEEDED}, yes) |
|||
include ${PLAT_COMMON_PATH}/fip_handler/ddr_fip/ddr_fip_io.mk |
|||
endif |
|||
|
|||
# For fuse-fip & fuse-programming
|
|||
ifeq (${FUSE_PROG}, 1) |
|||
include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk |
|||
endif |
|||
|
|||
ifeq (${IMG_LOADR_NEEDED},yes) |
|||
include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk |
|||
endif |
|||
|
|||
# Adding source files for the above selected drivers.
|
|||
include ${PLAT_DRIVERS_PATH}/drivers.mk |
|||
|
|||
# Adding SoC specific files
|
|||
include ${PLAT_COMMON_PATH}/soc_errata/errata.mk |
|||
|
|||
PLAT_INCLUDES += ${NV_STORAGE_INCLUDES}\
|
|||
${WARM_RST_INCLUDES} |
|||
|
|||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
|
|||
${WARM_RST_BL31_SOURCES}\
|
|||
${PSCI_SOURCES}\
|
|||
${SIPSVC_SOURCES}\
|
|||
${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S |
|||
|
|||
PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
|
|||
${PLAT_SOC_PATH}/aarch64/${SOC}_helpers.S\
|
|||
${NV_STORAGE_SOURCES}\
|
|||
${WARM_RST_BL_COMM_SOURCES}\
|
|||
${PLAT_SOC_PATH}/soc.c |
|||
|
|||
ifeq (${TEST_BL31}, 1) |
|||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S \
|
|||
${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S |
|||
endif |
|||
|
|||
BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
|
|||
${TBBR_SOURCES}\
|
|||
${FUSE_SOURCES} |
|||
|
|||
# Adding TFA setup files
|
|||
include ${PLAT_PATH}/common/setup/common.mk |
|||
Loading…
Reference in new issue