danh-arm
8 years ago
committed by
GitHub
GitHub
13 changed files with 1084 additions and 7 deletions
@ -0,0 +1,132 @@ |
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __CSS_SCMI_H__ |
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#define __CSS_SCMI_H__ |
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#include <bakery_lock.h> |
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#include <stddef.h> |
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#include <stdint.h> |
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/* Supported SCMI Protocol Versions */ |
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#define SCMI_PWR_DMN_PROTO_VER MAKE_SCMI_VERSION(1, 0) |
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#define SCMI_SYS_PWR_PROTO_VER MAKE_SCMI_VERSION(1, 0) |
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#define GET_SCMI_MAJOR_VER(ver) (((ver) >> 16) & 0xffff) |
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#define GET_SCMI_MINOR_VER(ver) ((ver) & 0xffff) |
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#define MAKE_SCMI_VERSION(maj, min) \ |
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((((maj) & 0xffff) << 16) | ((min) & 0xffff)) |
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/* Macro to check if the driver is compatible with the SCMI version reported */ |
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#define is_scmi_version_compatible(drv, scmi) \ |
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((GET_SCMI_MAJOR_VER(drv) == GET_SCMI_MAJOR_VER(scmi)) && \ |
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(GET_SCMI_MINOR_VER(drv) <= GET_SCMI_MINOR_VER(scmi))) |
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/* SCMI Protocol identifiers */ |
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#define SCMI_PWR_DMN_PROTO_ID 0x11 |
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#define SCMI_SYS_PWR_PROTO_ID 0x12 |
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/* Mandatory messages IDs for all SCMI protocols */ |
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#define SCMI_PROTO_VERSION_MSG 0x0 |
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#define SCMI_PROTO_ATTR_MSG 0x1 |
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#define SCMI_PROTO_MSG_ATTR_MSG 0x2 |
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/* SCMI power domain management protocol message IDs */ |
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#define SCMI_PWR_STATE_SET_MSG 0x4 |
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#define SCMI_PWR_STATE_GET_MSG 0x5 |
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/* SCMI system power management protocol message IDs */ |
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#define SCMI_SYS_PWR_STATE_SET_MSG 0x3 |
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#define SCMI_SYS_PWR_STATE_GET_MSG 0x4 |
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/* Helper macros for system power management protocol commands */ |
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/*
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* Macros to describe the bit-fields of the `attribute` of system power domain |
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* protocol PROTOCOL_MSG_ATTRIBUTE message. |
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*/ |
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#define SYS_PWR_ATTR_WARM_RESET_SHIFT 31 |
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#define SCMI_SYS_PWR_WARM_RESET_SUPPORTED (1U << SYS_PWR_ATTR_WARM_RESET_SHIFT) |
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#define SYS_PWR_ATTR_SUSPEND_SHIFT 30 |
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#define SCMI_SYS_PWR_SUSPEND_SUPPORTED (1 << SYS_PWR_ATTR_SUSPEND_SHIFT) |
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/*
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* Macros to describe the bit-fields of the `flags` parameter of system power |
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* domain protocol SYSTEM_POWER_STATE_SET message. |
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*/ |
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#define SYS_PWR_SET_GRACEFUL_REQ_SHIFT 0 |
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#define SCMI_SYS_PWR_GRACEFUL_REQ (1 << SYS_PWR_SET_GRACEFUL_REQ_SHIFT) |
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#define SCMI_SYS_PWR_FORCEFUL_REQ (0 << SYS_PWR_SET_GRACEFUL_REQ_SHIFT) |
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/*
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* Macros to describe the `system_state` parameter of system power |
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* domain protocol SYSTEM_POWER_STATE_SET message. |
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*/ |
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#define SCMI_SYS_PWR_SHUTDOWN 0x0 |
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#define SCMI_SYS_PWR_COLD_RESET 0x1 |
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#define SCMI_SYS_PWR_WARM_RESET 0x2 |
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#define SCMI_SYS_PWR_POWER_UP 0x3 |
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#define SCMI_SYS_PWR_SUSPEND 0x4 |
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/* SCMI Error code definitions */ |
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#define SCMI_E_QUEUED 1 |
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#define SCMI_E_SUCCESS 0 |
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#define SCMI_E_NOT_SUPPORTED -1 |
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#define SCMI_E_INVALID_PARAM -2 |
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#define SCMI_E_DENIED -3 |
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#define SCMI_E_NOT_FOUND -4 |
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#define SCMI_E_OUT_OF_RANGE -5 |
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#define SCMI_E_BUSY -6 |
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/*
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* SCMI driver platform information. The details of the doorbell mechanism |
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* can be found in the SCMI specification. |
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*/ |
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typedef struct scmi_channel_plat_info { |
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/* SCMI mailbox memory */ |
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uintptr_t scmi_mbx_mem; |
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/* The door bell register address */ |
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uintptr_t db_reg_addr; |
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/* The bit mask that need to be preserved when ringing doorbell */ |
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uint32_t db_preserve_mask; |
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/* The bit mask that need to be set to ring doorbell */ |
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uint32_t db_modify_mask; |
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} scmi_channel_plat_info_t; |
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/*
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* Structure to represent an SCMI channel. |
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*/ |
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typedef struct scmi_channel { |
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scmi_channel_plat_info_t *info; |
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/* The lock for channel access */ |
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bakery_lock_t *lock; |
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/* Indicate whether the channel is initialized */ |
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int is_initialized; |
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} scmi_channel_t; |
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/* External Common API */ |
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void *scmi_init(scmi_channel_t *ch); |
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int scmi_proto_msg_attr(void *p, uint32_t proto_id, uint32_t command_id, |
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uint32_t *attr); |
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int scmi_proto_version(void *p, uint32_t proto_id, uint32_t *version); |
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/*
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* Power domain protocol commands. Refer to the SCMI specification for more |
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* details on these commands. |
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*/ |
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int scmi_pwr_state_set(void *p, uint32_t domain_id, uint32_t scmi_pwr_state); |
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int scmi_pwr_state_get(void *p, uint32_t domain_id, uint32_t *scmi_pwr_state); |
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/*
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* System power management protocol commands. Refer SCMI specification for more |
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* details on these commands. |
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*/ |
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int scmi_sys_pwr_state_set(void *p, uint32_t flags, uint32_t system_state); |
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int scmi_sys_pwr_state_get(void *p, uint32_t *system_state); |
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#endif /* __CSS_SCMI_H__ */ |
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@ -0,0 +1,196 @@ |
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <arch_helpers.h> |
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#include <assert.h> |
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#include <debug.h> |
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#include "scmi.h" |
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#include "scmi_private.h" |
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/*
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* Private helper function to get exclusive access to SCMI channel. |
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*/ |
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void scmi_get_channel(scmi_channel_t *ch) |
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{ |
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assert(ch->lock); |
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bakery_lock_get(ch->lock); |
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/* Make sure any previous command has finished */ |
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assert(SCMI_IS_CHANNEL_FREE( |
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((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status)); |
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} |
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/*
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* Private helper function to transfer ownership of channel from AP to SCP. |
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*/ |
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void scmi_send_sync_command(scmi_channel_t *ch) |
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{ |
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mailbox_mem_t *mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); |
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SCMI_MARK_CHANNEL_BUSY(mbx_mem->status); |
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/*
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* Ensure that any write to the SCMI payload area is seen by SCP before |
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* we write to the doorbell register. If these 2 writes were reordered |
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* by the CPU then SCP would read stale payload data |
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*/ |
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dmbst(); |
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SCMI_RING_DOORBELL(ch->info->db_reg_addr, ch->info->db_modify_mask, |
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ch->info->db_preserve_mask); |
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/*
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* Ensure that the write to the doorbell register is ordered prior to |
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* checking whether the channel is free. |
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*/ |
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dmbsy(); |
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/* Wait for channel to be free */ |
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while (!SCMI_IS_CHANNEL_FREE(mbx_mem->status)) |
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; |
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/*
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* Ensure that any read to the SCMI payload area is done after reading |
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* mailbox status. If these 2 reads were reordered then the CPU would |
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* read invalid payload data |
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*/ |
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dmbld(); |
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} |
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/*
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* Private helper function to release exclusive access to SCMI channel. |
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*/ |
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void scmi_put_channel(scmi_channel_t *ch) |
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{ |
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/* Make sure any previous command has finished */ |
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assert(SCMI_IS_CHANNEL_FREE( |
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((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status)); |
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assert(ch->lock); |
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bakery_lock_release(ch->lock); |
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} |
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/*
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* API to query the SCMI protocol version. |
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*/ |
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int scmi_proto_version(void *p, uint32_t proto_id, uint32_t *version) |
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{ |
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mailbox_mem_t *mbx_mem; |
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int token = 0, ret; |
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scmi_channel_t *ch = (scmi_channel_t *)p; |
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validate_scmi_channel(ch); |
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scmi_get_channel(ch); |
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mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); |
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mbx_mem->msg_header = SCMI_MSG_CREATE(proto_id, SCMI_PROTO_VERSION_MSG, |
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token); |
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mbx_mem->len = SCMI_PROTO_VERSION_MSG_LEN; |
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mbx_mem->flags = SCMI_FLAG_RESP_POLL; |
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scmi_send_sync_command(ch); |
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/* Get the return values */ |
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SCMI_PAYLOAD_RET_VAL2(mbx_mem->payload, ret, *version); |
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assert(mbx_mem->len == SCMI_PROTO_VERSION_RESP_LEN); |
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assert(token == SCMI_MSG_GET_TOKEN(mbx_mem->msg_header)); |
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scmi_put_channel(ch); |
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return ret; |
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} |
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/*
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* API to query the protocol message attributes for a SCMI protocol. |
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*/ |
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int scmi_proto_msg_attr(void *p, uint32_t proto_id, |
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uint32_t command_id, uint32_t *attr) |
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{ |
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mailbox_mem_t *mbx_mem; |
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int token = 0, ret; |
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scmi_channel_t *ch = (scmi_channel_t *)p; |
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validate_scmi_channel(ch); |
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scmi_get_channel(ch); |
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mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); |
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mbx_mem->msg_header = SCMI_MSG_CREATE(proto_id, |
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SCMI_PROTO_MSG_ATTR_MSG, token); |
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mbx_mem->len = SCMI_PROTO_MSG_ATTR_MSG_LEN; |
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mbx_mem->flags = SCMI_FLAG_RESP_POLL; |
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SCMI_PAYLOAD_ARG1(mbx_mem->payload, command_id); |
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scmi_send_sync_command(ch); |
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/* Get the return values */ |
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SCMI_PAYLOAD_RET_VAL2(mbx_mem->payload, ret, *attr); |
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assert(mbx_mem->len == SCMI_PROTO_MSG_ATTR_RESP_LEN); |
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assert(token == SCMI_MSG_GET_TOKEN(mbx_mem->msg_header)); |
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scmi_put_channel(ch); |
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return ret; |
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} |
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/*
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* SCMI Driver initialization API. Returns initialized channel on success |
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* or NULL on error. The return type is an opaque void pointer. |
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*/ |
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void *scmi_init(scmi_channel_t *ch) |
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{ |
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uint32_t version; |
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int ret; |
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assert(ch && ch->info); |
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assert(ch->info->db_reg_addr); |
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assert(ch->info->db_modify_mask); |
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assert(ch->info->db_preserve_mask); |
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assert(ch->lock); |
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bakery_lock_init(ch->lock); |
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ch->is_initialized = 1; |
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ret = scmi_proto_version(ch, SCMI_PWR_DMN_PROTO_ID, &version); |
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if (ret != SCMI_E_SUCCESS) { |
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WARN("SCMI power domain protocol version message failed"); |
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goto error; |
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} |
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if (!is_scmi_version_compatible(SCMI_PWR_DMN_PROTO_VER, version)) { |
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WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x", |
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version, SCMI_PWR_DMN_PROTO_VER); |
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goto error; |
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} |
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VERBOSE("SCMI power domain protocol version 0x%x detected\n", version); |
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ret = scmi_proto_version(ch, SCMI_SYS_PWR_PROTO_ID, &version); |
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if ((ret != SCMI_E_SUCCESS)) { |
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WARN("SCMI system power protocol version message failed"); |
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goto error; |
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} |
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if (!is_scmi_version_compatible(SCMI_SYS_PWR_PROTO_VER, version)) { |
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WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x", |
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version, SCMI_SYS_PWR_PROTO_VER); |
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goto error; |
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} |
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VERBOSE("SCMI system power management protocol version 0x%x detected\n", |
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version); |
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INFO("SCMI driver initialized\n"); |
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return (void *)ch; |
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error: |
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ch->is_initialized = 0; |
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return NULL; |
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} |
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@ -0,0 +1,148 @@ |
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __CSS_SCMI_PRIVATE_H__ |
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#define __CSS_SCMI_PRIVATE_H__ |
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/*
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* SCMI power domain management protocol message and response lengths. It is |
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* calculated as sum of length in bytes of the message header (4) and payload |
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* area (the number of bytes of parameters or return values in the payload). |
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*/ |
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#define SCMI_PROTO_VERSION_MSG_LEN 4 |
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#define SCMI_PROTO_VERSION_RESP_LEN 12 |
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#define SCMI_PROTO_MSG_ATTR_MSG_LEN 8 |
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#define SCMI_PROTO_MSG_ATTR_RESP_LEN 12 |
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#define SCMI_PWR_STATE_SET_MSG_LEN 16 |
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#define SCMI_PWR_STATE_SET_RESP_LEN 8 |
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#define SCMI_PWR_STATE_GET_MSG_LEN 8 |
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#define SCMI_PWR_STATE_GET_RESP_LEN 12 |
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#define SCMI_SYS_PWR_STATE_SET_MSG_LEN 12 |
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#define SCMI_SYS_PWR_STATE_SET_RESP_LEN 8 |
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#define SCMI_SYS_PWR_STATE_GET_MSG_LEN 4 |
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#define SCMI_SYS_PWR_STATE_GET_RESP_LEN 12 |
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/* SCMI message header format bit field */ |
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#define SCMI_MSG_ID_SHIFT 0 |
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#define SCMI_MSG_ID_WIDTH 8 |
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#define SCMI_MSG_ID_MASK ((1 << SCMI_MSG_ID_WIDTH) - 1) |
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#define SCMI_MSG_TYPE_SHIFT 8 |
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#define SCMI_MSG_TYPE_WIDTH 2 |
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#define SCMI_MSG_TYPE_MASK ((1 << SCMI_MSG_TYPE_WIDTH) - 1) |
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#define SCMI_MSG_PROTO_ID_SHIFT 10 |
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#define SCMI_MSG_PROTO_ID_WIDTH 8 |
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#define SCMI_MSG_PROTO_ID_MASK ((1 << SCMI_MSG_PROTO_ID_WIDTH) - 1) |
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#define SCMI_MSG_TOKEN_SHIFT 18 |
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#define SCMI_MSG_TOKEN_WIDTH 10 |
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#define SCMI_MSG_TOKEN_MASK ((1 << SCMI_MSG_TOKEN_WIDTH) - 1) |
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/* SCMI mailbox flags */ |
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#define SCMI_FLAG_RESP_POLL 0 |
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#define SCMI_FLAG_RESP_INT 1 |
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/* SCMI power domain protocol `POWER_STATE_SET` message flags */ |
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#define SCMI_PWR_STATE_SET_FLAG_SYNC 0 |
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#define SCMI_PWR_STATE_SET_FLAG_ASYNC 1 |
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/*
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* Helper macro to create an SCMI message header given protocol, message id |
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* and token. |
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*/ |
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#define SCMI_MSG_CREATE(protocol, msg_id, token) \ |
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((((protocol) & SCMI_MSG_PROTO_ID_MASK) << SCMI_MSG_PROTO_ID_SHIFT) | \ |
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(((msg_id) & SCMI_MSG_ID_MASK) << SCMI_MSG_ID_SHIFT) | \ |
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(((token) & SCMI_MSG_TOKEN_MASK) << SCMI_MSG_TOKEN_SHIFT)) |
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/* Helper macro to get the token from a SCMI message header */ |
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#define SCMI_MSG_GET_TOKEN(msg) \ |
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(((msg) >> SCMI_MSG_TOKEN_SHIFT) & SCMI_MSG_TOKEN_MASK) |
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/* SCMI Channel Status bit fields */ |
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#define SCMI_CH_STATUS_RES0_MASK 0xFFFFFFFE |
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#define SCMI_CH_STATUS_FREE_SHIFT 0 |
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#define SCMI_CH_STATUS_FREE_WIDTH 1 |
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#define SCMI_CH_STATUS_FREE_MASK ((1 << SCMI_CH_STATUS_FREE_WIDTH) - 1) |
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/* Helper macros to check and write the channel status */ |
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#define SCMI_IS_CHANNEL_FREE(status) \ |
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(!!(((status) >> SCMI_CH_STATUS_FREE_SHIFT) & SCMI_CH_STATUS_FREE_MASK)) |
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#define SCMI_MARK_CHANNEL_BUSY(status) do { \ |
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assert(SCMI_IS_CHANNEL_FREE(status)); \ |
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(status) &= ~(SCMI_CH_STATUS_FREE_MASK << \ |
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SCMI_CH_STATUS_FREE_SHIFT); \ |
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} while (0) |
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/* Helper macros to copy arguments to the mailbox payload */ |
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#define SCMI_PAYLOAD_ARG1(payld_arr, arg1) \ |
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mmio_write_32((uintptr_t)&payld_arr[0], arg1) |
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#define SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2) do { \ |
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SCMI_PAYLOAD_ARG1(payld_arr, arg1); \ |
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mmio_write_32((uintptr_t)&payld_arr[1], arg2); \ |
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} while (0) |
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#define SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3) do { \ |
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SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2); \ |
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mmio_write_32((uintptr_t)&payld_arr[2], arg3); \ |
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} while (0) |
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/* Helper macros to read return values from the mailbox payload */ |
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#define SCMI_PAYLOAD_RET_VAL1(payld_arr, val1) \ |
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(val1) = mmio_read_32((uintptr_t)&payld_arr[0]) |
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#define SCMI_PAYLOAD_RET_VAL2(payld_arr, val1, val2) do { \ |
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SCMI_PAYLOAD_RET_VAL1(payld_arr, val1); \ |
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(val2) = mmio_read_32((uintptr_t)&payld_arr[1]); \ |
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} while (0) |
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#define SCMI_PAYLOAD_RET_VAL3(payld_arr, val1, val2, val3) do { \ |
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SCMI_PAYLOAD_RET_VAL2(payld_arr, val1, val2); \ |
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(val3) = mmio_read_32((uintptr_t)&payld_arr[2]); \ |
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} while (0) |
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/* Helper macro to ring doorbell */ |
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#define SCMI_RING_DOORBELL(addr, modify_mask, preserve_mask) do { \ |
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uint32_t db = mmio_read_32(addr) & (preserve_mask); \ |
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mmio_write_32(addr, db | (modify_mask)); \ |
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} while (0) |
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/*
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* Private data structure for representing the mailbox memory layout. Refer |
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* the SCMI specification for more details. |
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*/ |
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typedef struct mailbox_mem { |
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uint32_t res_a; /* Reserved */ |
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volatile uint32_t status; |
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uint64_t res_b; /* Reserved */ |
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uint32_t flags; |
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volatile uint32_t len; |
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uint32_t msg_header; |
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uint32_t payload[]; |
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} mailbox_mem_t; |
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/* Private APIs for use within SCMI driver */ |
|||
void scmi_get_channel(scmi_channel_t *ch); |
|||
void scmi_send_sync_command(scmi_channel_t *ch); |
|||
void scmi_put_channel(scmi_channel_t *ch); |
|||
|
|||
static inline void validate_scmi_channel(scmi_channel_t *ch) |
|||
{ |
|||
assert(ch && ch->is_initialized); |
|||
assert(ch->info && ch->info->scmi_mbx_mem); |
|||
} |
|||
|
|||
#endif /* __CSS_SCMI_PRIVATE_H__ */ |
|||
@ -0,0 +1,84 @@ |
|||
/*
|
|||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#include <arch_helpers.h> |
|||
#include <assert.h> |
|||
#include <debug.h> |
|||
#include "scmi.h" |
|||
#include "scmi_private.h" |
|||
|
|||
/*
|
|||
* API to set the SCMI power domain power state. |
|||
*/ |
|||
int scmi_pwr_state_set(void *p, uint32_t domain_id, |
|||
uint32_t scmi_pwr_state) |
|||
{ |
|||
mailbox_mem_t *mbx_mem; |
|||
int token = 0, ret; |
|||
|
|||
/*
|
|||
* Only asynchronous mode of `set power state` command is allowed on |
|||
* application processors. |
|||
*/ |
|||
uint32_t pwr_state_set_msg_flag = SCMI_PWR_STATE_SET_FLAG_ASYNC; |
|||
scmi_channel_t *ch = (scmi_channel_t *)p; |
|||
|
|||
validate_scmi_channel(ch); |
|||
|
|||
scmi_get_channel(ch); |
|||
|
|||
mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); |
|||
mbx_mem->msg_header = SCMI_MSG_CREATE(SCMI_PWR_DMN_PROTO_ID, |
|||
SCMI_PWR_STATE_SET_MSG, token); |
|||
mbx_mem->len = SCMI_PWR_STATE_SET_MSG_LEN; |
|||
mbx_mem->flags = SCMI_FLAG_RESP_POLL; |
|||
SCMI_PAYLOAD_ARG3(mbx_mem->payload, pwr_state_set_msg_flag, |
|||
domain_id, scmi_pwr_state); |
|||
|
|||
scmi_send_sync_command(ch); |
|||
|
|||
/* Get the return values */ |
|||
SCMI_PAYLOAD_RET_VAL1(mbx_mem->payload, ret); |
|||
assert(mbx_mem->len == SCMI_PWR_STATE_SET_RESP_LEN); |
|||
assert(token == SCMI_MSG_GET_TOKEN(mbx_mem->msg_header)); |
|||
|
|||
scmi_put_channel(ch); |
|||
|
|||
return ret; |
|||
} |
|||
|
|||
/*
|
|||
* API to get the SCMI power domain power state. |
|||
*/ |
|||
int scmi_pwr_state_get(void *p, uint32_t domain_id, |
|||
uint32_t *scmi_pwr_state) |
|||
{ |
|||
mailbox_mem_t *mbx_mem; |
|||
int token = 0, ret; |
|||
scmi_channel_t *ch = (scmi_channel_t *)p; |
|||
|
|||
validate_scmi_channel(ch); |
|||
|
|||
scmi_get_channel(ch); |
|||
|
|||
mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); |
|||
mbx_mem->msg_header = SCMI_MSG_CREATE(SCMI_PWR_DMN_PROTO_ID, |
|||
SCMI_PWR_STATE_GET_MSG, token); |
|||
mbx_mem->len = SCMI_PWR_STATE_GET_MSG_LEN; |
|||
mbx_mem->flags = SCMI_FLAG_RESP_POLL; |
|||
SCMI_PAYLOAD_ARG1(mbx_mem->payload, domain_id); |
|||
|
|||
scmi_send_sync_command(ch); |
|||
|
|||
/* Get the return values */ |
|||
SCMI_PAYLOAD_RET_VAL2(mbx_mem->payload, ret, *scmi_pwr_state); |
|||
assert(mbx_mem->len == SCMI_PWR_STATE_GET_RESP_LEN); |
|||
assert(token == SCMI_MSG_GET_TOKEN(mbx_mem->msg_header)); |
|||
|
|||
scmi_put_channel(ch); |
|||
|
|||
return ret; |
|||
} |
|||
@ -0,0 +1,74 @@ |
|||
/*
|
|||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#include <arch_helpers.h> |
|||
#include <assert.h> |
|||
#include <debug.h> |
|||
#include "scmi.h" |
|||
#include "scmi_private.h" |
|||
|
|||
/*
|
|||
* API to set the SCMI system power state |
|||
*/ |
|||
int scmi_sys_pwr_state_set(void *p, uint32_t flags, uint32_t system_state) |
|||
{ |
|||
mailbox_mem_t *mbx_mem; |
|||
int token = 0, ret; |
|||
scmi_channel_t *ch = (scmi_channel_t *)p; |
|||
|
|||
validate_scmi_channel(ch); |
|||
|
|||
scmi_get_channel(ch); |
|||
|
|||
mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); |
|||
mbx_mem->msg_header = SCMI_MSG_CREATE(SCMI_SYS_PWR_PROTO_ID, |
|||
SCMI_SYS_PWR_STATE_SET_MSG, token); |
|||
mbx_mem->len = SCMI_SYS_PWR_STATE_SET_MSG_LEN; |
|||
mbx_mem->flags = SCMI_FLAG_RESP_POLL; |
|||
SCMI_PAYLOAD_ARG2(mbx_mem->payload, flags, system_state); |
|||
|
|||
scmi_send_sync_command(ch); |
|||
|
|||
/* Get the return values */ |
|||
SCMI_PAYLOAD_RET_VAL1(mbx_mem->payload, ret); |
|||
assert(mbx_mem->len == SCMI_SYS_PWR_STATE_SET_RESP_LEN); |
|||
assert(token == SCMI_MSG_GET_TOKEN(mbx_mem->msg_header)); |
|||
|
|||
scmi_put_channel(ch); |
|||
|
|||
return ret; |
|||
} |
|||
|
|||
/*
|
|||
* API to get the SCMI system power state |
|||
*/ |
|||
int scmi_sys_pwr_state_get(void *p, uint32_t *system_state) |
|||
{ |
|||
mailbox_mem_t *mbx_mem; |
|||
int token = 0, ret; |
|||
scmi_channel_t *ch = (scmi_channel_t *)p; |
|||
|
|||
validate_scmi_channel(ch); |
|||
|
|||
scmi_get_channel(ch); |
|||
|
|||
mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); |
|||
mbx_mem->msg_header = SCMI_MSG_CREATE(SCMI_SYS_PWR_PROTO_ID, |
|||
SCMI_SYS_PWR_STATE_GET_MSG, token); |
|||
mbx_mem->len = SCMI_SYS_PWR_STATE_GET_MSG_LEN; |
|||
mbx_mem->flags = SCMI_FLAG_RESP_POLL; |
|||
|
|||
scmi_send_sync_command(ch); |
|||
|
|||
/* Get the return values */ |
|||
SCMI_PAYLOAD_RET_VAL2(mbx_mem->payload, ret, *system_state); |
|||
assert(mbx_mem->len == SCMI_SYS_PWR_STATE_GET_RESP_LEN); |
|||
assert(token == SCMI_MSG_GET_TOKEN(mbx_mem->msg_header)); |
|||
|
|||
scmi_put_channel(ch); |
|||
|
|||
return ret; |
|||
} |
|||
@ -0,0 +1,385 @@ |
|||
/*
|
|||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#include <arch_helpers.h> |
|||
#include <assert.h> |
|||
#include <css_def.h> |
|||
#include <css_pm.h> |
|||
#include <debug.h> |
|||
#include <plat_arm.h> |
|||
#include <platform.h> |
|||
#include <string.h> |
|||
#include "../scmi/scmi.h" |
|||
#include "css_scp.h" |
|||
|
|||
/*
|
|||
* This file implements the SCP helper functions using SCMI protocol. |
|||
*/ |
|||
|
|||
/*
|
|||
* SCMI power state parameter bit field encoding for ARM CSS platforms. |
|||
* |
|||
* 31 20 19 16 15 12 11 8 7 4 3 0 |
|||
* +-------------------------------------------------------------+ |
|||
* | SBZ | Max level | Level 3 | Level 2 | Level 1 | Level 0 | |
|||
* | | | state | state | state | state | |
|||
* +-------------------------------------------------------------+ |
|||
* |
|||
* `Max level` encodes the highest level that has a valid power state |
|||
* encoded in the power state. |
|||
*/ |
|||
#define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 16 |
|||
#define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4 |
|||
#define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \ |
|||
((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1) |
|||
#define SCMI_SET_PWR_STATE_MAX_PWR_LVL(pwr_state, max_lvl) \ |
|||
(pwr_state) |= ((max_lvl) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK) \ |
|||
<< SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT |
|||
#define SCMI_GET_PWR_STATE_MAX_PWR_LVL(pwr_state) \ |
|||
(((pwr_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \ |
|||
& SCMI_PWR_STATE_MAX_PWR_LVL_MASK) |
|||
|
|||
#define SCMI_PWR_STATE_LVL_WIDTH 4 |
|||
#define SCMI_PWR_STATE_LVL_MASK \ |
|||
((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1) |
|||
#define SCMI_SET_PWR_STATE_LVL(pwr_state, lvl, lvl_state) \ |
|||
(pwr_state) |= ((lvl_state) & SCMI_PWR_STATE_LVL_MASK) \ |
|||
<< (SCMI_PWR_STATE_LVL_WIDTH * (lvl)) |
|||
#define SCMI_GET_PWR_STATE_LVL(pwr_state, lvl) \ |
|||
(((pwr_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (lvl))) & \ |
|||
SCMI_PWR_STATE_LVL_MASK) |
|||
|
|||
/*
|
|||
* The SCMI power state enumeration for a power domain level |
|||
*/ |
|||
typedef enum { |
|||
scmi_power_state_off = 0, |
|||
scmi_power_state_on = 1, |
|||
scmi_power_state_sleep = 2, |
|||
} scmi_power_state_t; |
|||
|
|||
/*
|
|||
* This mapping array has to be exported by the platform. Each element at |
|||
* a given index maps that core to an SCMI power domain. |
|||
*/ |
|||
extern uint32_t plat_css_core_pos_to_scmi_dmn_id_map[]; |
|||
|
|||
/*
|
|||
* The global handle for invoking the SCMI driver APIs after the driver |
|||
* has been initialized. |
|||
*/ |
|||
void *scmi_handle; |
|||
|
|||
/* The SCMI channel global object */ |
|||
static scmi_channel_t scmi_channel; |
|||
|
|||
ARM_INSTANTIATE_LOCK |
|||
|
|||
/*
|
|||
* Helper function to suspend a CPU power domain and its parent power domains |
|||
* if applicable. |
|||
*/ |
|||
void css_scp_suspend(const psci_power_state_t *target_state) |
|||
{ |
|||
int lvl, ret; |
|||
uint32_t scmi_pwr_state = 0; |
|||
|
|||
/* At least power domain level 0 should be specified to be suspended */ |
|||
assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
|||
ARM_LOCAL_STATE_OFF); |
|||
|
|||
/* Check if power down at system power domain level is requested */ |
|||
if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { |
|||
/* Issue SCMI command for SYSTEM_SUSPEND */ |
|||
ret = scmi_sys_pwr_state_set(scmi_handle, |
|||
SCMI_SYS_PWR_FORCEFUL_REQ, |
|||
SCMI_SYS_PWR_SUSPEND); |
|||
if (ret != SCMI_E_SUCCESS) { |
|||
ERROR("SCMI system power domain suspend return 0x%x unexpected\n", |
|||
ret); |
|||
panic(); |
|||
} |
|||
return; |
|||
} |
|||
|
|||
/*
|
|||
* If we reach here, then assert that power down at system power domain |
|||
* level is running. |
|||
*/ |
|||
assert(target_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] == |
|||
ARM_LOCAL_STATE_RUN); |
|||
|
|||
/* For level 0, specify `scmi_power_state_sleep` as the power state */ |
|||
SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, ARM_PWR_LVL0, |
|||
scmi_power_state_sleep); |
|||
|
|||
for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { |
|||
if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) |
|||
break; |
|||
|
|||
assert(target_state->pwr_domain_state[lvl] == |
|||
ARM_LOCAL_STATE_OFF); |
|||
/*
|
|||
* Specify `scmi_power_state_off` as power state for higher |
|||
* levels. |
|||
*/ |
|||
SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, |
|||
scmi_power_state_off); |
|||
} |
|||
|
|||
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); |
|||
|
|||
ret = scmi_pwr_state_set(scmi_handle, |
|||
plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], |
|||
scmi_pwr_state); |
|||
|
|||
if (ret != SCMI_E_SUCCESS) { |
|||
ERROR("SCMI set power state command return 0x%x unexpected\n", |
|||
ret); |
|||
panic(); |
|||
} |
|||
} |
|||
|
|||
/*
|
|||
* Helper function to turn off a CPU power domain and its parent power domains |
|||
* if applicable. |
|||
*/ |
|||
void css_scp_off(const psci_power_state_t *target_state) |
|||
{ |
|||
int lvl = 0, ret; |
|||
uint32_t scmi_pwr_state = 0; |
|||
|
|||
/* At-least the CPU level should be specified to be OFF */ |
|||
assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
|||
ARM_LOCAL_STATE_OFF); |
|||
|
|||
/* PSCI CPU OFF cannot be used to turn OFF system power domain */ |
|||
assert(target_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] == |
|||
ARM_LOCAL_STATE_RUN); |
|||
|
|||
for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { |
|||
if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) |
|||
break; |
|||
|
|||
assert(target_state->pwr_domain_state[lvl] == |
|||
ARM_LOCAL_STATE_OFF); |
|||
SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, |
|||
scmi_power_state_off); |
|||
} |
|||
|
|||
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); |
|||
|
|||
ret = scmi_pwr_state_set(scmi_handle, |
|||
plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], |
|||
scmi_pwr_state); |
|||
|
|||
if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { |
|||
ERROR("SCMI set power state command return 0x%x unexpected\n", |
|||
ret); |
|||
panic(); |
|||
} |
|||
} |
|||
|
|||
/*
|
|||
* Helper function to turn ON a CPU power domain and its parent power domains |
|||
* if applicable. |
|||
*/ |
|||
void css_scp_on(u_register_t mpidr) |
|||
{ |
|||
int lvl = 0, ret; |
|||
uint32_t scmi_pwr_state = 0; |
|||
|
|||
for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) |
|||
SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, |
|||
scmi_power_state_on); |
|||
|
|||
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); |
|||
|
|||
ret = scmi_pwr_state_set(scmi_handle, |
|||
plat_css_core_pos_to_scmi_dmn_id_map[plat_core_pos_by_mpidr(mpidr)], |
|||
scmi_pwr_state); |
|||
|
|||
if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { |
|||
ERROR("SCMI set power state command return 0x%x unexpected\n", |
|||
ret); |
|||
panic(); |
|||
} |
|||
} |
|||
|
|||
/*
|
|||
* Helper function to get the power state of a power domain node as reported |
|||
* by the SCP. |
|||
*/ |
|||
int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) |
|||
{ |
|||
int ret, cpu_idx; |
|||
uint32_t scmi_pwr_state = 0, lvl_state; |
|||
|
|||
/* We don't support get power state at the system power domain level */ |
|||
if ((power_level > PLAT_MAX_PWR_LVL) || |
|||
(power_level == CSS_SYSTEM_PWR_DMN_LVL)) { |
|||
WARN("Invalid power level %u specified for SCMI get power state\n", |
|||
power_level); |
|||
return PSCI_E_INVALID_PARAMS; |
|||
} |
|||
|
|||
cpu_idx = plat_core_pos_by_mpidr(mpidr); |
|||
assert(cpu_idx > -1); |
|||
|
|||
ret = scmi_pwr_state_get(scmi_handle, |
|||
plat_css_core_pos_to_scmi_dmn_id_map[cpu_idx], |
|||
&scmi_pwr_state); |
|||
|
|||
if (ret != SCMI_E_SUCCESS) { |
|||
WARN("SCMI get power state command return 0x%x unexpected\n", |
|||
ret); |
|||
return PSCI_E_INVALID_PARAMS; |
|||
} |
|||
|
|||
/*
|
|||
* Find the maximum power level described in the get power state |
|||
* command. If it is less than the requested power level, then assume |
|||
* the requested power level is ON. |
|||
*/ |
|||
if (SCMI_GET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state) < power_level) |
|||
return HW_ON; |
|||
|
|||
lvl_state = SCMI_GET_PWR_STATE_LVL(scmi_pwr_state, power_level); |
|||
if (lvl_state == scmi_power_state_on) |
|||
return HW_ON; |
|||
|
|||
assert((lvl_state == scmi_power_state_off) || |
|||
(lvl_state == scmi_power_state_sleep)); |
|||
return HW_OFF; |
|||
} |
|||
|
|||
/*
|
|||
* Helper function to shutdown the system via SCMI. |
|||
*/ |
|||
void __dead2 css_scp_sys_shutdown(void) |
|||
{ |
|||
int ret; |
|||
|
|||
/*
|
|||
* Disable GIC CPU interface to prevent pending interrupt from waking |
|||
* up the AP from WFI. |
|||
*/ |
|||
plat_arm_gic_cpuif_disable(); |
|||
|
|||
/*
|
|||
* Issue SCMI command for SYSTEM_SHUTDOWN. First issue a graceful |
|||
* request and if that fails force the request. |
|||
*/ |
|||
ret = scmi_sys_pwr_state_set(scmi_handle, |
|||
SCMI_SYS_PWR_FORCEFUL_REQ, |
|||
SCMI_SYS_PWR_SHUTDOWN); |
|||
if (ret != SCMI_E_SUCCESS) { |
|||
ERROR("SCMI system power domain shutdown return 0x%x unexpected\n", |
|||
ret); |
|||
panic(); |
|||
} |
|||
|
|||
wfi(); |
|||
ERROR("CSS System Shutdown: operation not handled.\n"); |
|||
panic(); |
|||
} |
|||
|
|||
/*
|
|||
* Helper function to reset the system via SCMI. |
|||
*/ |
|||
void __dead2 css_scp_sys_reboot(void) |
|||
{ |
|||
int ret; |
|||
|
|||
/*
|
|||
* Disable GIC CPU interface to prevent pending interrupt from waking |
|||
* up the AP from WFI. |
|||
*/ |
|||
plat_arm_gic_cpuif_disable(); |
|||
|
|||
/*
|
|||
* Issue SCMI command for SYSTEM_REBOOT. First issue a graceful |
|||
* request and if that fails force the request. |
|||
*/ |
|||
ret = scmi_sys_pwr_state_set(scmi_handle, |
|||
SCMI_SYS_PWR_FORCEFUL_REQ, |
|||
SCMI_SYS_PWR_COLD_RESET); |
|||
if (ret != SCMI_E_SUCCESS) { |
|||
ERROR("SCMI system power domain reset return 0x%x unexpected\n", |
|||
ret); |
|||
panic(); |
|||
} |
|||
|
|||
wfi(); |
|||
ERROR("CSS System Reset: operation not handled.\n"); |
|||
panic(); |
|||
} |
|||
|
|||
scmi_channel_plat_info_t plat_css_scmi_plat_info = { |
|||
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, |
|||
.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, |
|||
.db_preserve_mask = 0xfffffffd, |
|||
.db_modify_mask = 0x2, |
|||
}; |
|||
|
|||
void plat_arm_pwrc_setup(void) |
|||
{ |
|||
scmi_channel.info = &plat_css_scmi_plat_info; |
|||
scmi_channel.lock = ARM_LOCK_GET_INSTANCE; |
|||
scmi_handle = scmi_init(&scmi_channel); |
|||
if (scmi_handle == NULL) { |
|||
ERROR("SCMI Initialization failed\n"); |
|||
panic(); |
|||
} |
|||
} |
|||
|
|||
/******************************************************************************
|
|||
* This function overrides the default definition for ARM platforms. Initialize |
|||
* the SCMI driver, query capability via SCMI and modify the PSCI capability |
|||
* based on that. |
|||
*****************************************************************************/ |
|||
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) |
|||
{ |
|||
uint32_t msg_attr; |
|||
int ret; |
|||
|
|||
assert(scmi_handle); |
|||
|
|||
/* Check that power domain POWER_STATE_SET message is supported */ |
|||
ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID, |
|||
SCMI_PWR_STATE_SET_MSG, &msg_attr); |
|||
if (ret != SCMI_E_SUCCESS) { |
|||
ERROR("Set power state command is not supported by SCMI\n"); |
|||
panic(); |
|||
} |
|||
|
|||
/*
|
|||
* Don't support PSCI NODE_HW_STATE call if SCMI doesn't support |
|||
* POWER_STATE_GET message. |
|||
*/ |
|||
ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID, |
|||
SCMI_PWR_STATE_GET_MSG, &msg_attr); |
|||
if (ret != SCMI_E_SUCCESS) |
|||
ops->get_node_hw_state = NULL; |
|||
|
|||
/* Check if the SCMI SYSTEM_POWER_STATE_SET message is supported */ |
|||
ret = scmi_proto_msg_attr(scmi_handle, SCMI_SYS_PWR_PROTO_ID, |
|||
SCMI_SYS_PWR_STATE_SET_MSG, &msg_attr); |
|||
if (ret != SCMI_E_SUCCESS) { |
|||
/* System power management operations are not supported */ |
|||
ops->system_off = NULL; |
|||
ops->system_reset = NULL; |
|||
ops->get_sys_suspend_power_state = NULL; |
|||
} else if (!(msg_attr & SCMI_SYS_PWR_SUSPEND_SUPPORTED)) { |
|||
/*
|
|||
* System power management protocol is available, but it does |
|||
* not support SYSTEM SUSPEND. |
|||
*/ |
|||
ops->get_sys_suspend_power_state = NULL; |
|||
} |
|||
|
|||
return ops; |
|||
} |
|||
Loading…
Reference in new issue