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@ -57,17 +57,13 @@ workaround_reset_end neoverse_n2, ERRATUM(2002655) |
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check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) |
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workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 |
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mrs x1, NEOVERSE_N2_CPUECTLR_EL1 |
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orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT |
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msr NEOVERSE_N2_CPUECTLR_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT |
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workaround_reset_end neoverse_n2, ERRATUM(2025414) |
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check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) |
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workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 |
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mrs x1, NEOVERSE_N2_CPUACTLR_EL1 |
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orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 |
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msr NEOVERSE_N2_CPUACTLR_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 |
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workaround_reset_end neoverse_n2, ERRATUM(2067956) |
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check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) |
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@ -107,27 +103,20 @@ check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) |
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workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 |
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/* Apply instruction patching sequence */ |
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mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 |
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orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 |
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msr NEOVERSE_N2_CPUACTLR5_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 |
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workaround_reset_end neoverse_n2, ERRATUM(2138958) |
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check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) |
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workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 |
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mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 |
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orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 |
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msr NEOVERSE_N2_CPUACTLR5_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 |
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workaround_reset_end neoverse_n2, ERRATUM(2189731) |
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check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) |
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workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 |
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/* Apply instruction patching sequence */ |
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mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 |
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orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 |
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msr NEOVERSE_N2_CPUACTLR5_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 |
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ldr x0, =0x2 |
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msr S3_6_c15_c8_0, x0 |
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ldr x0, =0x10F600E000 |
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@ -141,29 +130,21 @@ workaround_reset_end neoverse_n2, ERRATUM(2242400) |
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check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) |
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workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 |
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/* Apply instruction patching sequence */ |
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mrs x1, NEOVERSE_N2_CPUACTLR_EL1 |
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orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 |
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msr NEOVERSE_N2_CPUACTLR_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 |
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workaround_reset_end neoverse_n2, ERRATUM(2242415) |
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check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) |
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workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 |
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/* Apply instruction patching sequence */ |
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mrs x1, NEOVERSE_N2_CPUACTLR_EL1 |
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orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 |
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msr NEOVERSE_N2_CPUACTLR_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 |
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workaround_reset_end neoverse_n2, ERRATUM(2280757) |
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check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) |
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workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 |
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/* Set bit 36 in ACTLR2_EL1 */ |
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mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 |
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orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 |
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msr NEOVERSE_N2_CPUACTLR2_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 |
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workaround_runtime_end neoverse_n2, ERRATUM(2326639) |
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check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) |
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@ -173,23 +154,18 @@ workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 |
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* ST to behave like PLD/PFRM LD and not cause |
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* invalidations to other PE caches. |
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*/ |
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mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 |
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orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 |
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msr NEOVERSE_N2_CPUACTLR2_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 |
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workaround_reset_end neoverse_n2, ERRATUM(2376738) |
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check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 0) |
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workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 |
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/*Set bit 40 in ACTLR2_EL1 */ |
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mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 |
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orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 |
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msr NEOVERSE_N2_CPUACTLR2_EL1, x1 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 |
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workaround_reset_end neoverse_n2, ERRATUM(2388450) |
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check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) |
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workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 |
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/* dsb before isb of power down sequence */ |
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dsb sy |
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@ -197,15 +173,13 @@ workaround_runtime_end neoverse_n2, ERRATUM(2743089) |
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check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) |
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workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 |
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#if IMAGE_BL31 |
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/* |
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* The Neoverse-N2 generic vectors are overridden to apply errata |
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* mitigation on exception entry from lower ELs. |
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*/ |
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adr x0, wa_cve_vbar_neoverse_n2 |
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msr vbar_el3, x0 |
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override_vector_table wa_cve_vbar_neoverse_n2 |
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#endif /* IMAGE_BL31 */ |
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workaround_reset_end neoverse_n2, CVE(2022,23960) |
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@ -226,54 +200,34 @@ cpu_reset_func_start neoverse_n2 |
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msr SSBS, xzr |
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1: |
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/* Force all cacheable atomic instructions to be near */ |
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mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 |
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orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 |
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msr NEOVERSE_N2_CPUACTLR2_EL1, x0 |
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sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 |
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#if ENABLE_FEAT_AMU |
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
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mrs x0, cptr_el3 |
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orr x0, x0, #TAM_BIT |
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msr cptr_el3, x0 |
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sysreg_bit_set cptr_el3, TAM_BIT |
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
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mrs x0, cptr_el2 |
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orr x0, x0, #TAM_BIT |
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msr cptr_el2, x0 |
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sysreg_bit_set cptr_el2, TAM_BIT |
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/* No need to enable the counters as this would be done at el3 exit */ |
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#endif |
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#if NEOVERSE_Nx_EXTERNAL_LLC |
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/* Some systems may have External LLC, core needs to be made aware */ |
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mrs x0, NEOVERSE_N2_CPUECTLR_EL1 |
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orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT |
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msr NEOVERSE_N2_CPUECTLR_EL1, x0 |
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sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT |
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#endif |
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cpu_reset_func_end neoverse_n2 |
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func neoverse_n2_core_pwr_dwn |
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#if ERRATA_N2_2326639 |
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mov x15, x30 |
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bl cpu_get_rev_var |
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bl erratum_neoverse_n2_2326639_wa |
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mov x30, x15 |
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#endif /* ERRATA_N2_2326639 */ |
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apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 |
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/* --------------------------------------------------- |
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* Enable CPU power down bit in power control register |
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* No need to do cache maintenance here. |
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* --------------------------------------------------- |
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*/ |
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mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 |
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orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT |
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msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 |
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#if ERRATA_N2_2743089 |
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mov x15, x30 |
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bl cpu_get_rev_var |
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bl erratum_neoverse_n2_2743089_wa |
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mov x30, x15 |
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#endif /* ERRATA_N2_2743089 */ |
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sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT |
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apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 |
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isb |
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ret |
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endfunc neoverse_n2_core_pwr_dwn |
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