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Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>pull/1856/head
Masahisa Kojima
6 years ago
11 changed files with 410 additions and 18 deletions
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <assert.h> |
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#include <arch_helpers.h> |
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#include <common/debug.h> |
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#include <drivers/arm/css/scmi.h> |
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#include "scmi_private.h" |
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#include "scmi_sq.h" |
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#include <sq_common.h> |
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/* SCMI messge ID to get the available DRAM region */ |
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#define SCMI_VENDOR_EXT_MEMINFO_GET_MSG 0x3 |
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/*
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* API to get the available DRAM region |
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*/ |
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int scmi_get_draminfo(void *p, struct draminfo *info) |
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{ |
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mailbox_mem_t *mbx_mem; |
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int token = 0, ret; |
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scmi_channel_t *ch = (scmi_channel_t *)p; |
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struct dram_info_resp response; |
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validate_scmi_channel(ch); |
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scmi_get_channel(ch); |
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mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); |
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mbx_mem->msg_header = SCMI_MSG_CREATE(SCMI_SYS_VENDOR_EXT_PROTO_ID, |
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SCMI_VENDOR_EXT_MEMINFO_GET_MSG, token); |
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mbx_mem->len = 8; |
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mbx_mem->flags = SCMI_FLAG_RESP_POLL; |
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scmi_send_sync_command(ch); |
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/*
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* Ensure that any read to the SCPI payload area is done after reading |
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* the MHU register. If these 2 reads were reordered then the CPU would |
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* read invalid payload data |
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*/ |
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dmbld(); |
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/* Get the return values */ |
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SCMI_PAYLOAD_RET_VAL1(mbx_mem->payload, ret); |
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memcpy(&response, (void *)mbx_mem->payload, sizeof(response)); |
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scmi_put_channel(ch); |
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*info = response.info; |
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return ret; |
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} |
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef SCMI_SQ_H |
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#define SCMI_SQ_H |
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#include <stddef.h> |
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#include <stdint.h> |
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#include <sq_common.h> |
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/* Structure to represent available DRAM region */ |
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struct dram_info_resp { |
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int status; |
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int reserved; |
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struct draminfo info; |
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}; |
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/* API to get the available DRAM region */ |
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int scmi_get_draminfo(void *p, struct draminfo *info); |
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#endif /* SCMI_SQ_H */ |
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <assert.h> |
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#include <string.h> |
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#include <arch_helpers.h> |
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#include <common/debug.h> |
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#include <drivers/arm/css/css_mhu_doorbell.h> |
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#include <drivers/arm/css/css_scp.h> |
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#include <drivers/arm/css/scmi.h> |
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#include <plat/arm/css/common/css_pm.h> |
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#include <plat/common/platform.h> |
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#include <platform_def.h> |
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#include <scmi_sq.h> |
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#include <sq_common.h> |
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/*
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* This file implements the SCP helper functions using SCMI protocol. |
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*/ |
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DEFINE_BAKERY_LOCK(sq_scmi_lock); |
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#define SQ_SCMI_LOCK_GET_INSTANCE (&sq_scmi_lock) |
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#define SQ_SCMI_PAYLOAD_BASE PLAT_SQ_SCP_COM_SHARED_MEM_BASE |
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#define MHU_CPU_INTR_S_SET_OFFSET 0x308 |
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const uint32_t sq_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = { |
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, |
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12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 |
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}; |
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static scmi_channel_plat_info_t sq_scmi_plat_info = { |
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.scmi_mbx_mem = SQ_SCMI_PAYLOAD_BASE, |
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.db_reg_addr = PLAT_SQ_MHU_BASE + MHU_CPU_INTR_S_SET_OFFSET, |
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.db_preserve_mask = 0xfffffffe, |
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.db_modify_mask = 0x1, |
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.ring_doorbell = &mhu_ring_doorbell, |
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}; |
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/*
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* SCMI power state parameter bit field encoding for SynQuacer platform. |
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* |
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* 31 20 19 16 15 12 11 8 7 4 3 0 |
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* +-------------------------------------------------------------+ |
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* | SBZ | Max level | Level 3 | Level 2 | Level 1 | Level 0 | |
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* | | | state | state | state | state | |
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* +-------------------------------------------------------------+ |
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* |
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* `Max level` encodes the highest level that has a valid power state |
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* encoded in the power state. |
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*/ |
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#define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 16 |
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#define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4 |
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#define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \ |
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((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1) |
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#define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level) \ |
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(_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\ |
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<< SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT |
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#define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state) \ |
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(((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \ |
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& SCMI_PWR_STATE_MAX_PWR_LVL_MASK) |
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#define SCMI_PWR_STATE_LVL_WIDTH 4 |
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#define SCMI_PWR_STATE_LVL_MASK \ |
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((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1) |
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#define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state) \ |
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(_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK) \ |
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<< (SCMI_PWR_STATE_LVL_WIDTH * (_level)) |
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#define SCMI_GET_PWR_STATE_LVL(_power_state, _level) \ |
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(((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) & \ |
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SCMI_PWR_STATE_LVL_MASK) |
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/*
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* The SCMI power state enumeration for a power domain level |
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*/ |
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typedef enum { |
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scmi_power_state_off = 0, |
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scmi_power_state_on = 1, |
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scmi_power_state_sleep = 2, |
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} scmi_power_state_t; |
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/*
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* The global handle for invoking the SCMI driver APIs after the driver |
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* has been initialized. |
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*/ |
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static void *sq_scmi_handle; |
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/* The SCMI channel global object */ |
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static scmi_channel_t channel; |
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/*
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* Helper function to turn off a CPU power domain and |
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* its parent power domains if applicable. |
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*/ |
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void sq_scmi_off(const struct psci_power_state *target_state) |
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{ |
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int lvl = 0, ret; |
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uint32_t scmi_pwr_state = 0; |
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/* At-least the CPU level should be specified to be OFF */ |
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assert(target_state->pwr_domain_state[SQ_PWR_LVL0] == |
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SQ_LOCAL_STATE_OFF); |
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for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { |
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if (target_state->pwr_domain_state[lvl] == SQ_LOCAL_STATE_RUN) |
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break; |
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assert(target_state->pwr_domain_state[lvl] == |
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SQ_LOCAL_STATE_OFF); |
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SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, |
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scmi_power_state_off); |
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} |
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SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); |
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ret = scmi_pwr_state_set(sq_scmi_handle, |
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sq_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], |
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scmi_pwr_state); |
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if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { |
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ERROR("SCMI set power state command return 0x%x unexpected\n", |
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ret); |
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panic(); |
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} |
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} |
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/*
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* Helper function to turn ON a CPU power domain and |
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*its parent power domains if applicable. |
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*/ |
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void sq_scmi_on(u_register_t mpidr) |
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{ |
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int lvl = 0, ret, core_pos; |
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uint32_t scmi_pwr_state = 0; |
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for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) |
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SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, |
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scmi_power_state_on); |
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SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); |
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core_pos = plat_core_pos_by_mpidr(mpidr); |
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assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT); |
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ret = scmi_pwr_state_set(sq_scmi_handle, |
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sq_core_pos_to_scmi_dmn_id_map[core_pos], |
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scmi_pwr_state); |
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if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { |
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ERROR("SCMI set power state command return 0x%x unexpected\n", |
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ret); |
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panic(); |
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} |
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} |
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void __dead2 sq_scmi_system_off(int state) |
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{ |
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int ret; |
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/*
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* Disable GIC CPU interface to prevent pending interrupt from waking |
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* up the AP from WFI. |
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*/ |
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sq_gic_cpuif_disable(); |
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/*
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* Issue SCMI command. First issue a graceful |
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* request and if that fails force the request. |
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*/ |
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ret = scmi_sys_pwr_state_set(sq_scmi_handle, |
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SCMI_SYS_PWR_FORCEFUL_REQ, |
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state); |
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if (ret != SCMI_E_SUCCESS) { |
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ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n", |
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state, ret); |
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panic(); |
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} |
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wfi(); |
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ERROR("SCMI set power state: operation not handled.\n"); |
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panic(); |
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} |
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/*
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* Helper function to reset the system via SCMI. |
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*/ |
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void __dead2 sq_scmi_sys_reboot(void) |
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{ |
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sq_scmi_system_off(SCMI_SYS_PWR_COLD_RESET); |
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} |
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static int scmi_ap_core_init(scmi_channel_t *ch) |
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{ |
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#if PROGRAMMABLE_RESET_ADDRESS |
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uint32_t version; |
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int ret; |
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ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version); |
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if (ret != SCMI_E_SUCCESS) { |
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WARN("SCMI AP core protocol version message failed\n"); |
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return -1; |
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} |
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if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) { |
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WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n", |
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version, SCMI_AP_CORE_PROTO_VER); |
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return -1; |
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} |
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INFO("SCMI AP core protocol version 0x%x detected\n", version); |
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#endif |
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return 0; |
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} |
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void __init plat_sq_pwrc_setup(void) |
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{ |
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channel.info = &sq_scmi_plat_info; |
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channel.lock = SQ_SCMI_LOCK_GET_INSTANCE; |
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sq_scmi_handle = scmi_init(&channel); |
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if (sq_scmi_handle == NULL) { |
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ERROR("SCMI Initialization failed\n"); |
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panic(); |
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} |
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if (scmi_ap_core_init(&channel) < 0) { |
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ERROR("SCMI AP core protocol initialization failed\n"); |
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panic(); |
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} |
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} |
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uint32_t sq_scmi_get_draminfo(struct draminfo *info) |
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{ |
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scmi_get_draminfo(sq_scmi_handle, info); |
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return 0; |
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} |
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@ -0,0 +1,21 @@ |
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <sq_common.h> |
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#include "sq_scpi.h" |
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/*
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* Helper function to get dram information from SCP. |
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*/ |
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uint32_t sq_scp_get_draminfo(struct draminfo *info) |
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{ |
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#if SQ_USE_SCMI_DRIVER |
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sq_scmi_get_draminfo(info); |
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#else |
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scpi_get_draminfo(info); |
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#endif |
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return 0; |
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} |
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