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@ -1,5 +1,5 @@ |
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/* |
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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@ -171,9 +171,19 @@ |
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do_cold_boot: |
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.endif /* _warm_boot_mailbox */ |
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/* --------------------------------------------------------------------- |
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* It is a cold boot. |
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* Perform any processor specific actions upon reset e.g. cache, TLB |
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* invalidations etc. |
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* --------------------------------------------------------------------- |
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*/ |
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bl reset_handler |
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el3_arch_init_common \_exception_vectors |
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.if \_secondary_cold_boot |
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/* ------------------------------------------------------------- |
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* It is a cold boot. |
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* Check if this is a primary or secondary CPU cold boot. |
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* The primary CPU will set up the platform while the |
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* secondaries are placed in a platform-specific state until the |
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* primary CPU performs the necessary actions to bring them out |
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@ -193,13 +203,10 @@ |
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.endif /* _secondary_cold_boot */ |
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/* --------------------------------------------------------------------- |
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* Perform any processor specific actions upon reset e.g. cache, TLB |
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* invalidations etc. |
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* Initialize memory now. Secondary CPU initialization won't get to this |
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* point. |
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* --------------------------------------------------------------------- |
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*/ |
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bl reset_handler |
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el3_arch_init_common \_exception_vectors |
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.if \_init_memory |
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bl platform_mem_init |
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