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@ -74,8 +74,17 @@ |
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/*******************************************************************************
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/*******************************************************************************
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* Platform specific page table and MMU setup constants |
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* Platform specific page table and MMU setup constants |
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******************************************************************************/ |
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******************************************************************************/ |
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) |
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) |
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#if (BL31_BASE >= (1ULL << 32U)) |
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/* Address range in High DDR and HBM memory range */ |
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#define PLAT_ADDR_SPACE_SHIFT U(42) |
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#else |
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/* Address range in OCM and Low DDR memory range */ |
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#define PLAT_ADDR_SPACE_SHIFT U(32) |
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#endif |
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << PLAT_ADDR_SPACE_SHIFT) |
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << PLAT_ADDR_SPACE_SHIFT) |
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#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) |
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#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) |
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