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refactor(cpus): convert Neoverse Poseidon to use CPU helpers 

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Icf406c05cdb8d62cd0f41a5f19ae5376707e69bd
pull/2000/head
Arvind Ram Prakash 1 year ago
parent
471e0b8b34
commit
b98eb2dc1d
1 changed files with 5 additions and 5 deletions
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  1. 10
      lib/cpus/aarch64/neoverse_poseidon.S

10
lib/cpus/aarch64/neoverse_poseidon.S
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@ -32,8 +32,8 @@ workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_2
* The Neoverse-poseidon generic vectors are overridden to apply errata * The Neoverse-poseidon generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs. * mitigation on exception entry from lower ELs.
*/ */
adr x0, wa_cve_vbar_neoverse_poseidon override_vector_table wa_cve_vbar_neoverse_poseidon
msr vbar_el3, x0
#endif /* IMAGE_BL31 */ #endif /* IMAGE_BL31 */
workaround_reset_end neoverse_poseidon, CVE(2022,23960) workaround_reset_end neoverse_poseidon, CVE(2022,23960)
@ -48,9 +48,9 @@ func neoverse_poseidon_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \
orr x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc neoverse_poseidon_core_pwr_dwn endfunc neoverse_poseidon_core_pwr_dwn

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