diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
index f8d1eaf85..f6f06a975 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
@@ -240,6 +240,10 @@
 #define NRD_CSS_SMMU_NCI_IO_BASE		ULL(0x280000000)
 #define NRD_CSS_SMMU_NCI_IO_SIZE		UL(0x60000000)
 
+/* GPC SMMU */
+#define NRD_CSS_GPC_SMMUV3_BASE			UL(0x300000000)
+#define NRD_CSS_GPC_SMMUV3_SIZE			UL(0x8000000)
+
 /* DRAM1 */
 #define NRD_CSS_DRAM1_BASE			UL(0x80000000)
 
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
index acbf9b371..1b92ec23b 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
@@ -75,6 +75,12 @@
 			ARM_SHARED_RAM_SIZE,				\
 			MT_MEMORY | MT_RW | EL3_PAS)
 
+#define NRD_CSS_GPC_SMMU_SMMUV3_MMAP					\
+		MAP_REGION_FLAT(					\
+			NRD_CSS_GPC_SMMUV3_BASE,			\
+			NRD_CSS_GPC_SMMUV3_SIZE,			\
+			MT_DEVICE | MT_RW | EL3_PAS)
+
 #define NRD_CSS_BL1_RW_MMAP						\
 		MAP_REGION_FLAT(					\
 			BL1_RW_BASE,					\
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
index fc4050803..f9a62ae3e 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
@@ -205,6 +205,9 @@
  * 0x280000000      |1.5GB   |L1 GPT |ANY    |SMMU & NCI IO            |
  * 0x2DFFFFFFF      |        |       |       |                         |
  * ---------------------------------------------------------------------
+ * 0x300000000      |128MB   |L1 GPT |ROOT   |GPC SMMU                 |
+ * 0x308000000      |        |       |       |                         |
+ * ---------------------------------------------------------------------
  * 0x8080000000     |6GB     |L1 GPT |ANY    |DRAM 2 CHIP 0            |
  * 0x81FFFFFFFF     |        |       |       |                         |
  * ---------------------------------------------------------------------
@@ -548,6 +551,12 @@
 			NRD_CSS_SMMU_NCI_IO_SIZE,			\
 			GPT_GPI_ANY)
 
+#define NRD_PAS_GPC_SMMUV3						\
+		GPT_MAP_REGION_GRANULE(					\
+			NRD_CSS_GPC_SMMUV3_BASE,			\
+			NRD_CSS_GPC_SMMUV3_SIZE,			\
+			GPT_GPI_ROOT)
+
 #define NRD_PAS_DRAM2_CHIP0						\
 		GPT_MAP_REGION_GRANULE(					\
 			NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 0),		\
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat3.c b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
index 4cd9420d3..7b9805224 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat3.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
@@ -59,6 +59,7 @@ const mmap_region_t plat_arm_mmap[] = {
 	NRD_ROS_SYSTEM_PERIPH_MMAP,
 	NRD_CSS_GPT_L1_DRAM_MMAP,
 	NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
+	NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
 	{0}
 };
 #endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
index c2dcb00e2..01bb76df8 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
@@ -72,6 +72,7 @@ BL31_SOURCES	+=	${NRD_CPU_SOURCES}				\
 			${RDFREMONT_BASE}/rdfremont_topology.c		\
 			${RDFREMONT_BASE}/rdfremont_plat_attest_token.c	\
 			${RDFREMONT_BASE}/rdfremont_realm_attest_key.c	\
+			drivers/arm/smmu/smmu_v3.c			\
 			drivers/cfi/v2m/v2m_flash.c			\
 			lib/utils/mem_region.c				\
 			plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
index a121061c3..29c2101f3 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
@@ -6,6 +6,8 @@
 
 #include <common/debug.h>
 #include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/smmu_v3.h>
+
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 #include <nrd_plat.h>
@@ -78,6 +80,19 @@ static uintptr_t rdfremontmc_multichip_gicr_frames[] = {
 
 void bl31_platform_setup(void)
 {
+	/*
+	 * Perform SMMUv3 GPT configuration for the GPC SMMU present in system
+	 * control block on RD-Fremont platforms. This SMMUv3 initialization is
+	 * not fatal.
+	 *
+	 * Don't perform smmuv3_security_init() for this instance of SMMUv3 as
+	 * the global aborts need not be configured to allow the components in
+	 * system control block send transations downstream to SMMUv3.
+	 */
+	if (smmuv3_init(NRD_CSS_GPC_SMMUV3_BASE) != 0) {
+		WARN("Failed initializing System SMMU.\n");
+	}
+
 #if (NRD_PLATFORM_VARIANT == 2)
 	int ret;
 	unsigned int i;