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refactor(cpu): use the updated IP name for Demeter CPU 

Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the updated IP name.

Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: Ia4bf45bf47807c06f4c966861230faea420d088f
pull/1988/merge
Joel Goddard 2 years ago
parent
e8f4ec1ab0
commit
bd063a73a8
5 changed files with 39 additions and 39 deletions
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  1. 2
      docs/security_advisories/security-advisory-tfv-9.rst
  2. 18
      include/lib/cpus/aarch64/neoverse_v2.h
  3. 54
      lib/cpus/aarch64/neoverse_v2.S
  4. 2
      plat/arm/board/fvp/platform.mk
  5. 2
      plat/arm/board/rdn2/platform.mk

2
docs/security_advisories/security-advisory-tfv-9.rst
View File

@ -85,7 +85,7 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
+----------------------+
| Neoverse-V1 |
+----------------------+
| Neoverse-Demeter |
| Neoverse-V2 |
+----------------------+
| Neoverse-Poseidon |
+----------------------+

18
include/lib/cpus/aarch64/neoverse_demeter.h → include/lib/cpus/aarch64/neoverse_v2.h
View File

@ -4,23 +4,23 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef NEOVERSE_DEMETER_H
#define NEOVERSE_DEMETER_H
#ifndef NEOVERSE_V2_H
#define NEOVERSE_V2_H
#define NEOVERSE_DEMETER_MIDR U(0x410FD4F0)
#define NEOVERSE_V2_MIDR U(0x410FD4F0)
/* Neoverse Demeter loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_DEMETER_BHB_LOOP_COUNT U(132)
/* Neoverse V2 loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_V2_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define NEOVERSE_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* NEOVERSE_DEMETER_H */
#endif /* NEOVERSE_V2_H */

54
lib/cpus/aarch64/neoverse_demeter.S → lib/cpus/aarch64/neoverse_v2.S
View File

@ -7,40 +7,40 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <neoverse_demeter.h>
#include <neoverse_v2.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse Demeter must be compiled with HW_ASSISTED_COHERENCY enabled"
#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_DEMETER_BHB_LOOP_COUNT, neoverse_demeter
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
#endif /* WORKAROUND_CVE_2022_23960 */
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func neoverse_demeter_core_pwr_dwn
func neoverse_v2_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, NEOVERSE_DEMETER_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_DEMETER_CPUPWRCTLR_EL1, x0
mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
isb
ret
endfunc neoverse_demeter_core_pwr_dwn
endfunc neoverse_v2_core_pwr_dwn
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
@ -51,27 +51,27 @@ func check_errata_cve_2022_23960
ret
endfunc check_errata_cve_2022_23960
func neoverse_demeter_reset_func
func neoverse_v2_reset_func
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Neoverse Demeter vectors are overridden to apply
* The Neoverse V2 vectors are overridden to apply
* errata mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_neoverse_demeter
adr x0, wa_cve_vbar_neoverse_v2
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb
ret
endfunc neoverse_demeter_reset_func
endfunc neoverse_v2_reset_func
#if REPORT_ERRATA
/*
* Errata printing function for Neoverse Demeter. Must follow AAPCS.
* Errata printing function for Neoverse V2. Must follow AAPCS.
*/
func neoverse_demeter_errata_report
func neoverse_v2_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
@ -81,15 +81,15 @@ func neoverse_demeter_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, neoverse_demeter, cve_2022_23960
report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc neoverse_demeter_errata_report
endfunc neoverse_v2_errata_report
#endif
/* ---------------------------------------------
* This function provides Neoverse Demeter-
* This function provides Neoverse V2-
* specific register information for crash
* reporting. It needs to return with x6
* pointing to a list of register names in ascii
@ -97,16 +97,16 @@ endfunc neoverse_demeter_errata_report
* reported.
* ---------------------------------------------
*/
.section .rodata.neoverse_demeter_regs, "aS"
neoverse_demeter_regs: /* The ascii list of register names to be reported */
.section .rodata.neoverse_v2_regs, "aS"
neoverse_v2_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func neoverse_demeter_cpu_reg_dump
adr x6, neoverse_demeter_regs
mrs x8, NEOVERSE_DEMETER_CPUECTLR_EL1
func neoverse_v2_cpu_reg_dump
adr x6, neoverse_v2_regs
mrs x8, NEOVERSE_V2_CPUECTLR_EL1
ret
endfunc neoverse_demeter_cpu_reg_dump
endfunc neoverse_v2_cpu_reg_dump
declare_cpu_ops neoverse_demeter, NEOVERSE_DEMETER_MIDR, \
neoverse_demeter_reset_func, \
neoverse_demeter_core_pwr_dwn
declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
neoverse_v2_reset_func, \
neoverse_v2_core_pwr_dwn

2
plat/arm/board/fvp/platform.mk
View File

@ -132,7 +132,7 @@ else
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/neoverse_demeter.S \
lib/cpus/aarch64/neoverse_v2.S \
lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a710.S \

2
plat/arm/board/rdn2/platform.mk
View File

@ -34,7 +34,7 @@ RDN2_BASE = plat/arm/board/rdn2
PLAT_INCLUDES += -I${RDN2_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_demeter.S
lib/cpus/aarch64/neoverse_v2.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c

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