fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name

Constants SD_SPEED_1_25_G and SD_SPEED_2_5_G refer to SerDes frequency,
which is 1.25x that of data rate, since 1000base-x and 2500base-x use
the 8b/10b encoding:

  mode         frequency   data rate
  1000base-x   1.25  GHz    1   Gbps
  2500base-x   3.125 GHz    2.5 Gbps

But the first constant refers to the frequency, while the second to the
data rate, which does not make sense.

Since the values in the specification refer to frequency, change the
name of the constant SD_SPEED_2_5_G to SD_SPEED_3_125_G to also refer to
the frequency, as SD_SPEED_1_25_G does.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I7670b45fa685aff93b3cafd84cf30d93620d8da1

drivers/marvell/comphy/phy-comphy-3700.c

@@ -422,8 +422,8 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
 		data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET;
 	} else if (mode == COMPHY_2500BASEX_MODE) {
 		/* 2500Base-X, SerDes speed 3.125G */
-		data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET;
-		data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET;
+		data |= SD_SPEED_3_125_G << GEN_RX_SEL_OFFSET;
+		data |= SD_SPEED_3_125_G << GEN_TX_SEL_OFFSET;
 	} else {
 		/* Other rates are not supported */
 		ERROR("unsupported SGMII speed on comphy lane%d\n",

drivers/marvell/comphy/phy-comphy-3700.h

@@ -237,7 +237,7 @@ enum {
 #define GEN_TX_SEL_MASK			(0xF << GEN_TX_SEL_OFFSET)
 #define PHY_RX_INIT_BIT			BIT(30)
 #define SD_SPEED_1_25_G			0x6
-#define SD_SPEED_2_5_G			0x8
+#define SD_SPEED_3_125_G		0x8
 
 /* COMPHY status reg:
  * lane0: PCIe/GbE0 PHY Status 1