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Add SiP service for multimedia & infra master to enable/disable MM & INFRA IOMMU in secure world TEST=build pass BUG=b:236339614 Signed-off-by: Chengci Xu <chengci.xu@mediatek.corp-partner.google.com> Change-Id: I4eb1fda6044cf2cb6c22c005cb2fa550906b71e9pull/1988/head
Chengci Xu
2 years ago
committed by
Bo-Chen Chen
Bo-Chen Chen
8 changed files with 348 additions and 0 deletions
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/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <mtk_iommu_plat.h> |
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#include <mtk_mmap_pool.h> |
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#include <platform_def.h> |
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/* mm iommu */ |
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#define SMI_L0_ID (0) |
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#define SMI_L1_ID (1) |
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#define SMI_L2_ID (2) |
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#define SMI_L3_ID (3) |
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#define SMI_L4_ID (4) |
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#define SMI_L5_ID (5) |
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#define SMI_L6_ID (6) |
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#define SMI_L7_ID (7) |
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#define SMI_L9_ID (8) |
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#define SMI_L10_ID (9) |
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#define SMI_L11A_ID (10) |
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#define SMI_L11B_ID (11) |
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#define SMI_L11C_ID (12) |
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#define SMI_L12_ID (13) |
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#define SMI_L13_ID (14) |
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#define SMI_L14_ID (15) |
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#define SMI_L15_ID (16) |
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#define SMI_L16A_ID (17) |
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#define SMI_L16B_ID (18) |
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#define SMI_L17A_ID (19) |
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#define SMI_L17B_ID (20) |
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#define SMI_L19_ID (21) |
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#define SMI_L21_ID (22) |
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#define SMI_L23_ID (23) |
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#define SMI_L27_ID (24) |
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#define SMI_L28_ID (25) |
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/* infra iommu */ |
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#define PERI_MST_PROT (0x710) |
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#define PERICFG_AO_IOMMU_1 (0x714) |
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#define MMU_DEV_PCIE_0 (0) |
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#define IFR_CFG_GROUP_NUM (1) |
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static struct mtk_smi_larb_config mt8188_larb_cfg[SMI_LARB_NUM] = { |
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[SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 7, 0), |
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[SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 7, 0), |
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[SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 5, 0), |
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[SMI_L3_ID] = LARB_CFG_ENTRY(SMI_LARB_3_BASE, 7, 0), |
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[SMI_L4_ID] = LARB_CFG_ENTRY(SMI_LARB_4_BASE, 7, 0), |
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[SMI_L5_ID] = LARB_CFG_ENTRY(SMI_LARB_5_BASE, 8, 0), |
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[SMI_L6_ID] = LARB_CFG_ENTRY(SMI_LARB_6_BASE, 4, 0), |
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[SMI_L7_ID] = LARB_CFG_ENTRY(SMI_LARB_7_BASE, 3, 0), |
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[SMI_L9_ID] = LARB_CFG_ENTRY(SMI_LARB_9_BASE, 25, 0), |
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[SMI_L10_ID] = LARB_CFG_ENTRY(SMI_LARB_10_BASE, 20, 0), |
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[SMI_L11A_ID] = LARB_CFG_ENTRY(SMI_LARB_11A_BASE, 30, 0), |
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[SMI_L11B_ID] = LARB_CFG_ENTRY(SMI_LARB_11B_BASE, 30, 0), |
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[SMI_L11C_ID] = LARB_CFG_ENTRY(SMI_LARB_11C_BASE, 30, 0), |
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[SMI_L12_ID] = LARB_CFG_ENTRY(SMI_LARB_12_BASE, 16, 0), |
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[SMI_L13_ID] = LARB_CFG_ENTRY(SMI_LARB_13_BASE, 24, 0), |
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[SMI_L14_ID] = LARB_CFG_ENTRY(SMI_LARB_14_BASE, 23, 0), |
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[SMI_L15_ID] = LARB_CFG_ENTRY(SMI_LARB_15_BASE, 19, 0), |
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[SMI_L16A_ID] = LARB_CFG_ENTRY(SMI_LARB_16A_BASE, 17, 0), |
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[SMI_L16B_ID] = LARB_CFG_ENTRY(SMI_LARB_16B_BASE, 17, 0), |
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[SMI_L17A_ID] = LARB_CFG_ENTRY(SMI_LARB_17A_BASE, 7, 0), |
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[SMI_L17B_ID] = LARB_CFG_ENTRY(SMI_LARB_17B_BASE, 7, 0), |
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/* venc nbm ports (5/6/11/15/16/17) to sram */ |
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[SMI_L19_ID] = LARB_CFG_ENTRY_WITH_PATH(SMI_LARB_19_BASE, 27, 0, 0x38860), |
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[SMI_L21_ID] = LARB_CFG_ENTRY(SMI_LARB_21_BASE, 11, 0), |
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[SMI_L23_ID] = LARB_CFG_ENTRY(SMI_LARB_23_BASE, 9, 0), |
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[SMI_L27_ID] = LARB_CFG_ENTRY(SMI_LARB_27_BASE, 4, 0), |
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[SMI_L28_ID] = LARB_CFG_ENTRY(SMI_LARB_28_BASE, 0, 0), |
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}; |
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static bool is_protected; |
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static uint32_t mt8188_ifr_mst_cfg_base[IFR_CFG_GROUP_NUM] = { |
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PERICFG_AO_BASE, |
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}; |
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static uint32_t mt8188_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = { |
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PERICFG_AO_IOMMU_1, |
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}; |
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static struct mtk_ifr_mst_config mt8188_ifr_mst_cfg[MMU_DEV_NUM] = { |
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[MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 18), |
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}; |
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struct mtk_smi_larb_config *g_larb_cfg = &mt8188_larb_cfg[0]; |
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struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8188_ifr_mst_cfg[0]; |
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uint32_t *g_ifr_mst_cfg_base = &mt8188_ifr_mst_cfg_base[0]; |
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uint32_t *g_ifr_mst_cfg_offs = &mt8188_ifr_mst_cfg_offs[0]; |
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/* Protect infra iommu enable setting registers as secure access. */ |
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void mtk_infra_iommu_enable_protect(void) |
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{ |
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if (!is_protected) { |
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mmio_write_32(PERICFG_AO_BASE + PERI_MST_PROT, 0xffffffff); |
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is_protected = true; |
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} |
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} |
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/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef IOMMU_PLAT_H |
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#define IOMMU_PLAT_H |
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#include <mtk_iommu_priv.h> |
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/* mm iommu */ |
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#define SMI_LARB_NUM (26) |
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extern struct mtk_smi_larb_config *g_larb_cfg; |
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/* infra iommu */ |
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#define MMU_DEV_NUM (1) |
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extern struct mtk_ifr_mst_config *g_ifr_mst_cfg; |
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extern uint32_t *g_ifr_mst_cfg_base; |
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extern uint32_t *g_ifr_mst_cfg_offs; |
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extern void mtk_infra_iommu_enable_protect(void); |
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#endif /* IOMMU_PLAT_H */ |
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/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef IOMMU_PRIV_H |
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#define IOMMU_PRIV_H |
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#include <common/debug.h> |
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#include <lib/mmio.h> |
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#include <mtk_sip_svc.h> |
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#define LARB_CFG_ENTRY(bs, p_nr, dom) \ |
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{ .base = (bs), .port_nr = (p_nr), \ |
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.dom_id = (dom), .to_sram = 0, } |
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#define LARB_CFG_ENTRY_WITH_PATH(bs, p_nr, dom, sram) \ |
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{ .base = (bs), .port_nr = (p_nr), \ |
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.dom_id = (dom), .to_sram = (sram), } |
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#define IFR_MST_CFG_ENTRY(idx, bit) \ |
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{ .cfg_addr_idx = (idx), .r_mmu_en_bit = (bit), } |
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enum IOMMU_ATF_CMD { |
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IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to enable iommu */ |
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IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */ |
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IOMMU_ATF_CMD_COUNT, |
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}; |
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struct mtk_smi_larb_config { |
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uint32_t base; |
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uint32_t port_nr; |
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uint32_t dom_id; |
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uint32_t to_sram; |
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uint32_t sec_en_msk; |
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}; |
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struct mtk_ifr_mst_config { |
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uint8_t cfg_addr_idx; |
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uint8_t r_mmu_en_bit; |
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}; |
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#endif /* IOMMU_PRIV_H */ |
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/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <stddef.h> |
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#include <mtk_iommu_plat.h> |
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/* defination */ |
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/* smi larb */ |
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#define SMI_LARB_NON_SEC_CON(port) (0x380 + ((port) << 2)) |
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#define PATH_SEL_MASK (0xf0000) /* to sram (INT) */ |
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#define SMI_LARB_SEC_CON_INT(port) (0xf00 + ((port) << 2)) |
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#define SMI_LARB_SEC_CON(port) (0xf80 + ((port) << 2)) |
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#define MMU_MASK BIT(0) |
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#define MMU_EN(en) ((!!(en)) << 0) |
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#define SEC_MASK BIT(1) |
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#define SEC_EN(en) ((!!(en)) << 1) |
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#define DOMAIN_MASK (0x1f << 4) |
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#define SMI_MMU_EN(port) (0x1 << (port)) |
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/* infra master */ |
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#define IFR_CFG_MMU_EN_MSK(r_bit) (0x3 << (r_bit)) |
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/* smi larb configure */ |
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/*
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* If multimedia security config is enabled, the SMI config register must be |
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* configurated in security world. |
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* And the SRAM path is also configurated here to enhance security. |
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*/ |
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static void mtk_smi_larb_port_config_to_sram( |
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const struct mtk_smi_larb_config *larb, |
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uint32_t port_id) |
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{ |
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mmio_clrbits_32(larb->base + SMI_LARB_SEC_CON_INT(port_id), |
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MMU_MASK | SEC_MASK | DOMAIN_MASK); |
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mmio_setbits_32(larb->base + SMI_LARB_NON_SEC_CON(port_id), |
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PATH_SEL_MASK); |
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} |
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static void mtk_smi_port_config(const struct mtk_smi_larb_config *larb, |
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uint32_t port_id, uint8_t mmu_en, uint8_t sec_en) |
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{ |
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mmio_clrsetbits_32(larb->base + SMI_LARB_SEC_CON(port_id), |
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MMU_MASK | SEC_MASK | DOMAIN_MASK, |
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MMU_EN(mmu_en) | SEC_EN(sec_en)); |
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} |
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static int mtk_smi_larb_port_config_sec(uint32_t larb_id, uint32_t mmu_en_msk) |
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{ |
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uint32_t port_id, port_nr; |
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const struct mtk_smi_larb_config *larb; |
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uint32_t to_sram; |
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uint8_t mmu_en; |
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if (larb_id >= SMI_LARB_NUM) { |
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return MTK_SIP_E_INVALID_PARAM; |
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} |
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larb = &g_larb_cfg[larb_id]; |
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port_nr = larb->port_nr; |
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to_sram = larb->to_sram; |
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for (port_id = 0; port_id < port_nr; port_id++) { |
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if ((to_sram & BIT(port_id)) > 0U) { |
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mtk_smi_larb_port_config_to_sram(larb, port_id); |
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continue; |
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} |
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mmu_en = !!(mmu_en_msk & SMI_MMU_EN(port_id)); |
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mtk_smi_port_config(larb, port_id, mmu_en, 0); |
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} |
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return MTK_SIP_E_SUCCESS; |
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} |
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static int mtk_infra_master_config_sec(uint32_t dev_id, uint32_t enable) |
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{ |
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const struct mtk_ifr_mst_config *ifr_cfg; |
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uint32_t reg_addr; |
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mtk_infra_iommu_enable_protect(); |
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if (dev_id >= MMU_DEV_NUM) { |
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return MTK_SIP_E_NOT_SUPPORTED; |
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} |
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ifr_cfg = &g_ifr_mst_cfg[dev_id]; |
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reg_addr = g_ifr_mst_cfg_base[(ifr_cfg->cfg_addr_idx)] + |
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g_ifr_mst_cfg_offs[(ifr_cfg->cfg_addr_idx)]; |
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if (enable > 0U) { |
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mmio_setbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit)); |
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} else { |
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mmio_clrbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit)); |
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} |
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return MTK_SIP_E_SUCCESS; |
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} |
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static u_register_t mtk_iommu_handler(u_register_t x1, u_register_t x2, |
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u_register_t x3, u_register_t x4, |
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void *handle, struct smccc_res *smccc_ret) |
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{ |
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uint32_t cmd_id = x1, mdl_id = x2, val = x3; |
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int ret = MTK_SIP_E_NOT_SUPPORTED; |
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(void)x4; |
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(void)handle; |
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switch (cmd_id) { |
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case IOMMU_ATF_CMD_CONFIG_SMI_LARB: |
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ret = mtk_smi_larb_port_config_sec(mdl_id, val); |
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break; |
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case IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU: |
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ret = mtk_infra_master_config_sec(mdl_id, val); |
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break; |
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default: |
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break; |
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} |
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return ret; |
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} |
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DECLARE_SMC_HANDLER(MTK_SIP_IOMMU_CONTROL, mtk_iommu_handler); |
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#
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# Copyright (c) 2022, MediaTek Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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LOCAL_DIR := $(call GET_LOCAL_DIR) |
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MODULE := mtk_iommu |
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LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_iommu_smc.c |
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LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/mtk_iommu_plat.c |
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PLAT_INCLUDES += -I${LOCAL_DIR} |
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PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC} |
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$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) |
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