Merge "fix(errata): workaround for Cortex-X2 erratum 2371105" into integration

docs/design/cpu-specific-build-macros.rst

@@ -545,6 +545,10 @@ For Cortex-X2, the following errata build flags are defined :
    Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU,
    it is fixed in r2p1.
 
+-  ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to
+   Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is fixed in r2p1.
+
 For Cortex-A510, the following errata build flags are defined :
 
 -  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

include/lib/cpus/aarch64/cortex_x2.h

@@ -39,6 +39,12 @@
 #define CORTEX_X2_CPUACTLR_EL1					S3_0_C15_C1_0
 #define CORTEX_X2_CPUACTLR_EL1_BIT_22				(ULL(1) << 22)
 
+/*******************************************************************************
+ * CPU Auxiliary Control Register 2 definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUACTLR2_EL1					S3_0_C15_C1_1
+#define CORTEX_X2_CPUACTLR2_EL1_BIT_40				(ULL(1) << 40)
+
 /*******************************************************************************
  * CPU Auxiliary Control Register 5 definitions
  ******************************************************************************/

lib/cpus/aarch64/cortex_x2.S

@@ -267,6 +267,34 @@ func check_errata_2147715
 	b	cpu_rev_var_range
 endfunc check_errata_2147715
 
+/* -------------------------------------------------------
+ * Errata Workaround for Cortex-X2 Erratum 2371105.
+ * This applies to revisions <= r2p0 and is fixed in r2p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * -------------------------------------------------------
+ */
+func errata_x2_2371105_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2371105
+	cbz	x0, 1f
+
+	/* Set bit 40 in CPUACTLR2_EL1 */
+	mrs	x1, CORTEX_X2_CPUACTLR2_EL1
+	orr	x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40
+	msr	CORTEX_X2_CPUACTLR2_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_x2_2371105_wa
+
+func check_errata_2371105
+	/* Applies to <= r2p0. */
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_2371105
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
@@ -304,6 +332,7 @@ func cortex_x2_errata_report
 	report_errata ERRATA_X2_2083908, cortex_x2, 2083908
 	report_errata ERRATA_X2_2147715, cortex_x2, 2147715
 	report_errata ERRATA_X2_2216384, cortex_x2, 2216384
+	report_errata ERRATA_X2_2371105, cortex_x2, 2371105
 	report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960
 	report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941
 
@@ -361,6 +390,11 @@ func cortex_x2_reset_func
 	bl	errata_x2_2147715_wa
 #endif
 
+#if ERRATA_X2_2371105
+	mov	x0, x18
+	bl	errata_x2_2371105_wa
+#endif
+
 #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
 	/*
 	 * The Cortex-X2 generic vectors are overridden to apply errata

lib/cpus/cpu-ops.mk

@@ -603,6 +603,10 @@ ERRATA_X2_2216384	?=0
 # only to revision r2p0 of the Cortex-X2 cpu, it is fixed in r2p1.
 ERRATA_X2_2147715	?=0
 
+# Flag to apply erratum 2371105 workaround during reset. This erratum applies
+# to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1.
+ERRATA_X2_2371105	?=0
+
 # Flag to apply erratum 1922240 workaround during reset. This erratum applies
 # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
 ERRATA_A510_1922240	?=0
@@ -1163,6 +1167,10 @@ $(eval $(call add_define,ERRATA_X2_2216384))
 $(eval $(call assert_boolean,ERRATA_X2_2147715))
 $(eval $(call add_define,ERRATA_X2_2147715))
 
+# Process ERRATA_X2_2371105 flag
+$(eval $(call assert_boolean,ERRATA_X2_2371105))
+$(eval $(call add_define,ERRATA_X2_2371105))
+
 # Process ERRATA_A510_1922240 flag
 $(eval $(call assert_boolean,ERRATA_A510_1922240))
 $(eval $(call add_define,ERRATA_A510_1922240))